Showing papers on "System bus published in 1970"

Error-detecting circuitry

Abstract: Error detection circuitry employs duplicate equal order binary registers and comparison circuitry for detecting and diagnosis of errors in data bits being transferred between the storage registers and a data bus.

Distributed logic memory cell for parallel cellular-logic processor

Abstract: In a parallel cellular logic processor including a program control unit and a plurality of logic memory cells, all data inputs, except intercell inputs, for any cell are channeled through common input coupling logic to a one-bit intracell bus. The coupling logic is enabled or disabled in accordance with predetermined combinations of states of program control signals and of a plurality of control flip-flop circuits within the cell. Those flip-flop circuits receive data signal inputs from the bus. The same bus also provides data inputs for a data flip-flop circuit and for a data store within the cell. Data input to the bus is provided by way of the coupling logic from a program-selected one of the data flip-flop circuit, the store, an external source, or from program. Additional logic allows communication among cells by way of selective interconnection of their respective intracell buses as determined by further program control signals.

Performance Evaluation of a RFID-Enabled Real Time Bus Dispatching System: Case study of the Bangkok bus system

Abstract: This paper aims to present and evaluate the performance of one of the first real-time bus dispatching system in Bangkok, Thailand. The proposed bus dispatching system receives the real-time bus location data from the RFID sensor network. The paper provides the background and brief description of both the hardware and architecture of the RFID sensor network and the real-time bus dispatching system. The bus dispatching system continuously monitors the status of each bus and updates its expected arrival time at the depot using the real-time data from the RFID sensor network. If the expected number of vehicles falls below the required level, then the bus dispatching system will adjust the service headway and vehicle/driver assignments to minimize the impact on the service headway. The system is implemented on one of a bus lines in Bangkok. The main focus of the paper is to evaluate the performance of the implemented system by comparing the bus service qualities before and after the implementation of the real-time bus dispatching system. One month bus service data both before and after the system deployment are used in the evaluation of the bus level of service. The result illustrates the potential real-life benefit of the real-time bus dispatching system despite the simplicity of the timetable adjustment strategy.

Operating Experience with a Modular Digital Data System for High Energy Physics

Abstract: A modular digital data system originally designed for magnetostrictive wire spark chambers has been expanded to include most digital high energy physics data. The system is built around a 12 bit data bus and has been implemented for a number of computers and other output devices. This paper summarizes three years of operating experience.

Bus coupler protection circuit

Abstract: A protection circuit for data bus transmission coupling circuits is provided to protect the coupling circuits from injury due to the application of abnormally long duration pulses. The protection circuit is responsive to data pulses to be transmitted via the coupling circuits and generates inhibit signals to inhibit the coupling circuits upon the occurrence of data pulses of greater than a prescribed duration.