Showing papers on "System bus published in 1972"

Bus oriented,modular,multiprocessing computer

Abstract: A multiprocessing computer is structured in modular form around a common control and data bus. Control functions for the various modules are distributed among the modules to facilitate system flexibility. Modules separate from the central processor handle input/output operations to free the central processor for data manipulation. The central processor includes circuitry for instruction and data pipelining, single, double and triple shifts, preadding and memory mapping and interleaving. The central processor also includes a read only memory look-up table for microprogramming instructions.

Bus transport system for selection information and data

Abstract: A switching unit and a computer system comprising such a switching unit so as to enable processor to converse with a free storage module of a group of processors and storage modules at substantially any given moment. The switching unit comprises a common selection bus for transporting selection information from a processor to a storage module, and a common input and output bus for transporting data between a processor and a storage module. The switching unit furthermore comprises priority circuits so as to deal with simultaneously received requests for the same bus in a given sequence. According to the invention the switching unit comprises registers for storing selection information and/or data, said registers being connected after and eventually also before the relevant common bus.

Data bus transmission line termination circuit

Abstract: A data bus transmission line termination circuit for connection either to the terminal end of a data bus or to an intermediate portion of the bus. The circuit is programmable to either a low-impedance state for connection to the terminal end of the data bus so as to provide an optimum terminating load for the bus, or to a high-impedance state for connection to an intermediate portion of the data bus so as not to load down the latter when so connected. The termination circuit is preferably formed on the same integrated circuit chip as the receiver circuit so as to be located adjacent the effective end of the total transmission line including the portion extending from the data bus proper through the connections and conductors of the board, card, module and chip to the receiver circuit on the chip.

Data processing memory system with bidirectional data bus

Abstract: A digital computer memory system having a bidirectional data bus for transmitting information in both directions between the memory unit and a central processing unit associated with the memory system. The system includes a bidirectional latch unit for maintaining on the data bus the integrity of the information previously transmitted to the memory unit during a WRITE operation so that the central processing unit may check the stored information for errors.

Bus system for interconnecting systems of a communication switching system

Abstract: A bus system arranged such that the number of interconnection points between subsystems or modules are substantially reduced so that interfacing costs likewise are reduced. The multiple for continuing the bus is located on an interface connector assembly which provides an interfacing between the bus cable and the subsystem or module, so that the continuity of the bus can be maintained, regardless of the system status of any subsystem or subsystems. Normally, with other similar bus systems, the continuity of the bus is disrupted if a subsystem is taken out of service. Furthermore, unlike many other bus systems, the bus can be extended in vertical and/or horizontal directions. The bus system also is such that the bus can be easily terminated by simply inserting a terminator card on the interface connector assembly, or it can be extended by withdrawing the terminator card and plugging in a bus jumper cable with a terminator card at the last module.

Multiprocessing system having means for partitioning into independent processing subsystems

Abstract: This disclosure relates to a multiprocessing system having a plurality of different units including processors, I/O controllers and the like which can be arranged into individual processing groups. A plurality of control buses are provided one for each group, each control bus being coupled to each unit of that group. A control bus configuration unit is provided to receive each of the individual control buses such that any one control bus can be connected to any of the other control buses. In this manner, the multiprocessing system can be partitioned into separate subsystems each of which includes one or more of such processing group.

Improved bus system for interconnecting subsystems of a communication switching system

Abstract: A bus system arranged such that the number of interconnection points between subsystems or modules are substantially reduced so that interfacing costs likewise are reduced. The multiple for continuing the bus is located on an interface connector card which provides an interfacing between the bus cable and the subsystem or module, so that the continuity of the bus can be maintained, regardless of the system status of any subsystem or subsystems. Normally, with other similar bus systems, the continuity of the bus is disrupted if a subsystem is taken out of service. Furthermore, unlike many other bus systems, the bus can be extended in vertical and/or horizontal directions. The bus system also is such that the bus can be easily terminated by simply inserting a terminator card on the interface connector card, or it can be extended by withdrawing the terminator card and plugging in a bus jumper cable with a terminator card at the last module.

Partitioned ramdom access memories for increasing throughput rate

Abstract: Multiplexed words on the data bus of a time-division switch are written into a random access memory system and thereafter distributed to predefined time slots on selected lines. To increase the throughput of the memory system, two sets of memories are assigned to each line, each memory having a storage area dedicated to each of the several time slots on the line. During each time-division frame consecutive ones of the data words on the bus are each written into an appropriate one of the storage areas in consecutive ones of the memories in one set. At the same time data is read out from the memories in the other set into the time slots on the line, all of the storage areas dedicated to a time slot being read out simultaneously.

Error testing and error localization in a modular data processing system

Abstract: In a modular data processing system wherein the individual processing units are linked with each other via a bus system and with a central control, a tester is provided in each processing unit. The tester includes a test reply information register, an address generator for generating the processing unit address, a compare circuit for comparing the address transferred from the control unit via the address bus and stored in the address register with the processing unit address, a pattern generator for terminating the address bus with a given bit pattern of correct parity, a parity check circuit for signalling parity errors on the address bus, and a parity circuit for generating the correct parity bit from the bit pattern on the data bus. The output bits of these parity circuits together with the generated processing unit address are fed to the test reply information register for transmission. The tester also includes a control circuit for controlling the transmission of the addresses, the data patterns, and the test reply information.

Bus control arrangement for a communication switching system

Abstract: The system has duplicate central processors, each having its own bus. Subsystem modules include program memory, data base memory, status detector, register-senders, markers, etc., each having one or more memory word stores. Bus interface units of identical construction are interposed between the subsystem modules and the busses. Some modules such as program memory are duplicated and each connected to one bus, while others are connected via their interface unit to both buses. All memory addresses are accessed from a processor via its bus, each address being effective to select only one interface unit, and the complete address being then passed to the subsystem module to read or write a data word. The bus comprises control conductors, and data conductors for both address and data in either direction. A bus control unit at the central processor provides an address cycle followed by a data cycle indicated by signals on the control conductors.

Loadflow computer and dc circuit modules employed therein for simulating ac electric power networks

Abstract: A hybrid loadflow computer arrangement includes a modularized analog network simulator and a digital computer which acquires and processes on-line data and operator data related to the power system for which a loadflow problem is being solved. The analog simulator includes modular circuits representative of power system busses and lines and the interface between the digital computer and the analog network simulator is provided by analog-to-digital and digital-to-analog converters and by line outage contact closure outputs. The hybrid arrangement operates iteratively, with the analog network simulator providing a bus voltage solution for a set of network simultaneous equations and the digital computer providing bus load and generation injection current calculations and convergence steering control. The modular bus and line circuits are interconnected to simulate the power system and operate stably in forcing currents and voltages to satisfy current and voltage laws to provide the bus voltage solution. Integrated circuit operational amplifiers are employed as error current integrators in bus modules and as voltage difference amplifiers in line modules.

Computer Control of the Indiana University Cyclotron Facility

Abstract: The control system for the Indiana University cyclotron facility is designed to provide monitoring and display of accelerator status, logging and display of operational history, automated beam diagnostics, and presetting of operational parameters, in addition to manual operator control.The operator interacts with a control console which incorporates alphanumeric display terminals, a graphic display, a digital plotter, and various analog input devices. The console is connected to the computer, rather than directly to the accelerator, and the computer acquires data from and sends control information to the accelerator by means of multiplexed ADC's, DAC's, stepping motors, etc. The console and control devices are linked to the computer via a network of modular digital multiplexers which are attached to a common bidirectional data bus. This approach provides decentralization of the interface and allows orderly growth of the system.The computer runs under control of a multiprogramming monitor which executes da...