Showing papers on "System bus published in 1976"

Reconfigurable data bus

Abstract: A digital data communication system having a plurality of digital nodal communication devices interconnected by a digital data bus in a fixed physical manner in which the data bus structure may be electrically reconfigured without physical modification of the digital data bus. The ability to reconfigure the digital data bus is accomplished by the insertion of a digital reconfigurable data bus module into the position on the digital data bus previously held by one of the digital nodal communication devices and the connection of the replaced digital nodal communication device to the digital reconfigurable data bus module. The digital reconfigurable data bus module contains a transceiver mechanism capable of receiving and transmitting digital information to and from the digital data bus, an adapter mechanism for communicating with the replaced digital nodal communication device and a switching mechanism capable of the multiple switching of data from the adapter section which is connected to the replaced digital nodal communication device to the transceiver section which is connected to the digital data bus. The digital reconfigurable data bus module allows a fixed configuration of nodal devices and connecting devices to provide the function of tree structured buses, ring structured buses, dedicated channels or combinations of any of them. The module facilitates the receipt, switching and retransmission of data on any selected bus pattern.

Data format converting apparatus for use in a digital data processor

Abstract: Data format converting apparatus is described for simultaneously converting multiple bytes of zoned decimal data to packed decimal data or vice versa In the preferred embodiment, this format converting apparatus is obtained by adding a minimum amount of additional circuitry to a multibyte flow-through type data shifter used for providing the normal data shifting operations in a digital data processor In particular, a zoned-decimal-to-packed-decimal conversion capability is provided by combining additional switching logic with the normal shifter switching logic for enabling the conductors for nonadjacent data fields on the shifter input data bus to be coupled to the conductors for adjacent data fields on the shifter output data bus A packed-decimal-to-zoned-decimal conversion capability is provided by adding further switching logic for enabling the conductors for adjacent data fields on the shifter input data bus to be coupled to the conductors for nonadjacent data fields on the shifter output data bus Control circuitry is provided for selectively enabling either normal data shifting operations or zoned-to-packed format conversion operations or packed-to-zoned format conversion operations The shifting and format converting hardware is organized so that implementation in the form of large-scale integration circuitry can be accomplished with a minimum number of integrated circuit chips and a minimum number of chip input/output connections per chip

Computer controlled distribution apparatus for distributing transactions to and from controlled machine tools having means independent of the computer for completing or stopping a tool function initiated by a computer transaction

Abstract: A system for controlling a plurality of machine tools in which the central processor communicates data transactions to and from a plurality of tool controllers, each of which is operatively associated with a machine tool. Each of the controllers comprises at least one machine tool control unit which is adapted to provide a digital output to the associated machine tool for controlling a particular tool function and/or for receiving from the machine tool a digital input indicative of a particular tool condition. The central processor has connected thereto a main multiple-channel data bus for conducting data transactions by transferring parallel bits of data to and from the processor. The system also includes a plurality of multiple-channel unit data buses, each of which is connected to one of the tool control units. Data distribution apparatus in the system couple the unit data buses to the main data bus from the processor and serve to distribute the processor transactions to and from the specific tool functions of the controlled machine tools. This data distribution apparatus includes means responsive to a set of of distribution signals from the central processor for selectively activating one of the tool control units and for selectively activating only the data path from the main data bus through the unit data bus which is connected to the particular selected tool control unit. The data distribution apparatus also includes means for maintaining only this activated path open through said main data bus to the central processor and for maintaining all other data paths through unit data buses which are connected to unselected tool control units closed until the central processor issues the next set of distribution signals for selectively activating another tool control unit. In accordance with another aspect of the system, at least one of said tool controllers has means for completing a tool function initiated by a data transaction from the central processor after the data transaction is completed and the processor is no longer in communication with said tool controller.

Data transfer control apparatus and method

Abstract: An improved data transfer apparatus and method is fabricated by multiplexing at least a portion of the address of the peripherals on the data bus. Data transfer is simplified by adopting identical control timing for the read and write cycles, setting up address and data information early within a cycle and synchronizing the output of such information on the output busses coupled to the peripherals. Data transfer control signals may be encoded to simplify read and write input/output and memory operations. The advantage of such improvements permits reduce component count, pin requirements and gives rise to an ability to incorporate more system functions on a single chip.

Data processing system including a program-executing secondary system controlling a program-executing primary system

Abstract: Disclosed is a primary data processing system comprised of, for example, a main store, a storage unit, an instruction unit, an execution unit, a console unit and a channel unit for performing primary system programs. The console unit includes a secondary digital computer for performing secondary programs which functions to observe and/or alter the primary system. The functions performable by the secondary system include altering the primary system control state, causing primary commands to be executed, controlling primary data and addresses, and scanning out primary information. The console is connected through a command bus, an address bus and a data bus to the controls and data paths of the channel unit, of the instruction unit and of the storage unit.

Apparatus for facilitating a cooperation between an executive computer and a reserve computer

Abstract: In a twin computer system a two computers are timed by a common clock generator of clock pulses and are connected to each other by a cable which introduces a time delay greater than a clock pulse period. The computers process in parallel units of data from a plurality of operational units with the first of the computers being the executive computer and the second the reserve computer. The computers are identical and each includes both a first function unit and a second function unit interconnected by a bus system including order and data buses. In addition to the computers and clock generator there is apparatus for initiating the operation of both computers in a given sequence and timing by starting the first computer to process data, and then starting the second computer to process data a given period of time after the starting of the first computer, and actively connecting unidirectionally via the cable the data bus of the first computer to the data bus of the second computer for a certain length of time whereby units of data being transferred from the first function unit of the first computer to the second function unit of the first computer are also transferred to the second function unit of the second computer which correspond to said second function unit of the first computer so that the second computer is initially loaded with data being processed by the first computer. The given period of time the second computer is started after the first computer is substantially equal to the time required to transfer signals representing data from the data bus of the first computer to the data bus of the second computer.

Microprocessor architecture with integrated interrupts and cycle steals prioritized channel

Abstract: A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one or more input/output devices; and a multiplexed cycle steal and interrupt request common poll bus. The storage and input/output devices communicate with and are controlled by the central processing unit over a looped, or unidirectional bus and control channel including a bus in, a bus out, an address and control bus, and a plurality of control lines. Bus out is operated to address the executable control store and main storage, and to provide data to the input/output devices and the local storage registers. Bus in is shared by the input/output devices and all storage devices and registers for transferring data and control information to the central processing unit. Bus in is also used by main storage to receive data from the input/output devices and from the local storage registers. The address and control bus addresses the input/output devices and the local storage registers, thus enabling overlapping of device or local storage data transfers with the accessing of executable control storage and main storage, and with instruction execution. The arithmetic and logic unit is time shared for data and input/output processing, register/register and storage/register transfers, shift operations, byte manipulations, and address modification. Both cycle steal and interrupt requests are received by the central processor on the common poll bus.

Asynchronous bidirectional interface with priority bus monitoring among contending controllers and echo from a terminator

Abstract: An interface which connects input/output (I/O) controllers to a data channel in a data processing system. A bidirectional priority bus is provided interconnecting the channel with the controllers. Each controller is assigned a priority level. When a controller requires service, it signals the channel over a common request line and the channel responds with a channel select signal. Each requesting controller gates a binary number corresponding to its priority level onto the common priority bus. Contending controllers resolve priority among themselves by monitoring the priority bus. If a controller detects a higher priority level than its own level on the bus it removes its priority number from the bus. The highest priority controller then activates an acknowledge signal and places its device address on a bidirectional data bus in response to a ready signal from the channel.

Central processing unit employing microprogrammable control for use in a data processing system

Abstract: A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. Included are capabilities for effective addressing, incrementing the program counter and computer instruction skips, all while the instruction register is being loaded from memory by direct connection of selected bits of the memory bus to the ROM buffer to derive a micro-instruction. Also included is a conditional skip condition allowing the processor to skip the next instruction by testing selected bits of the instruction register which manipulates the micro-code for this purpose. Another capability is that of hardware structuring to readily accommodate WCS. Other capabilities provide for bit and byte manipulation, allowing the micro-instruction to readily load constants into the ALU, and for marking purposes. Data path connections provide for selective connection of the register file and the ALU output to the memory bus dependent upon existing memory bus and data bus communication with the memory. The above functions are accomplished with a fifty-six bit micro-instruction format impelmented with a sixteen bit word length, which allows for a flexible instruction set for a microprogrammed processor enabling a system to be designed to span the range from a minicomputer to a large processor.

Computer controlled distribution apparatus for distributing transactions to and from controlled machines tools

Abstract: A system for controlling a plurality of machine tools in which the central processor communicates data transactions to and from a plurality of tool controllers, each of which is operatively associated with a machine tool. Each of the controllers comprises at least one machine tool control unit which is adapted to provide a digital output to the associated machine tool for controlling a particular tool function and/or for receiving from the machine tool a digital input indicative of a particular tool condition. The central processor has connected thereto a main multiple-channel data bus for conducting data transactions by transferring parallel bits of data to and from the processor. The system also includes a plurality of multiple-channel unit data buses, each of which is connected to one of the tool control units. Data distribution apparatus in the system couple the unit data buses to the main data bus from the processor and serve to distribute the processor transactions to and from the specific tool functions of the controlled machine tools. This data distribution apparatus includes means responsive to a set of distribution signals from the central processor for selectively activating one of the tool control units and for selectively activating only the data path from the main data bus through the unit data bus which is connected to the particular selected tool control unit. The data distribution apparatus also includes means for maintaining only this activated path open through said main data bus to the central processor and for maintaining all other data paths through unit data buses which are connected to unselected tool control units closed until the central processor issues the next set of distribution signals for selectively activating another tool control unit. In accordance with another aspect of the system, at least one of said tool controllers has means for completing a tool function initiated by a data transaction from the central processor after the data transaction is completed and the processor is no longer in communication with said tool controller.

Method and apparatus for the two-way transmission of pulses

Abstract: In a method and apparatus for the two-way transmission of pulses between a plurality of out-stations generally connected to a common power supply network and at least one control unit, the data is applied to the power supply network using pulse code modulation so that the power supply network serves as a data bus bar between the out-stations and the control unit. A multiplexing of the data applied to the network permits individual communication between an out-station and the control unit during an assigned time slot with the power supply frequency being used for synchronizing the timing of the multiplex system.

Apparatus and method for generating timing signals for latched type memories

Abstract: Apparatus and a method for generating timing signals to be utilized in latched type memories only when the address signals are valid. A CAS signal is generated in response to an RAS signal via a device which tracks the worst case delay of memory address signals and does not permit the application of the CAS signal to memory until the worst case delay of the memory address signals has been accounted for. A memory array is comprised of any combination of latched or non-latched tri-state memories. The latched memories are coupled to a data bus utilizing conventional TTL circuits in combination with a power driver to simulate conventional tri-state buffer circuits. When the power driver/drivers remove(s) power from TTL circuits, the tri-state characteristics are simulated; whereas when the power driver applies power to the TTL circuits, they operate in their normal mode and present a normal impedance between the data bus and data-out lines of the memory array.

Power strobing to achieve a tri state

Abstract: Apparatus and a method for coupling and uncoupling data-read lines of a memory array to a data bus. The data read-out lines of a memory array which is comprised of any combination of latched or non-latched tri-state memories are coupled to the data bus utilizing a conventional TTL circuit in combination with a power driver to simulate a tri-state buffer circuit. When the power driver removes power from the TTL circuit, a tri-state circuit is simulated; whereas when the power driver applies power to the TTL circuit, it operates in its normal mode and a normal impedance is presented between the data bus and the data-out lines of the memory array.

Microprocessor system having a single central processing unit shared by a plurality of subsystems each having a memory

Abstract: A microprocessor system wherein a plurality of programs shares a single central processing unit. A first subsystem includes a memory having a program counter for indicating the point of execution of a program and a data pointer indicating the location in memory of data processed by the program in execution. At least one other subsystem includes a memory having a program counter for indicating the point of execution of a program and a data pointer indicating the location in memory of data being processed by the program in execution in that subsystem. A console control module is interconnected with the system data bus and the first and second subsystems, and controls operation of the central processing unit with each subsystem. The subsystem not connected to the central processing unit indicates the point of interruption of program execution with the program counter and indicates the location of data being processed by the interrupted program.

Interrupt status register for interface adaptor chip

Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, the data direction register and a data register. Data from the peripheral data bus the data direction register and the control register are transferred via the output bus to the data bus buffers. Control circuits include an interrupt/status logic circuit for transmitting control signals to and receiving interrupt signals from a peripheral unit coupled to the interface circuit.

Self-memorizing data bus system for random access data transfer

Abstract: A data bus system is disclosed for transferring data from one process area to another without synchronizing bus input and output functions. Data is driven onto the bus when available. When data is not being actively driven onto the bus, the bus will latch to its last driven state. The data may then be randomly accessed.

Apparatus and method for composing digital information on a data bus

Abstract: Logical and arithmetic shifts, rotations, and compositions of digital words can be performed directly on the data bus by use of registers which are selectively coupled to the data bus through bidirectional devices. The registers may be buffered latches having a tri-stated buffered output so that the contents of the register will not be altered by stray charges stored in the distributed capacitance of the selected data bus line.

Interval timer arrangement in a microprocessor system

Abstract: An interval timer in a MOS IC microprocessor system uses a countdown register of as many stages as the data bus lines (8) but effectively doubles the capacity of that register, without increasing the number of data bus lines or repetitive loading, by interposing a prescale divide-down register between the system clock and the countdown register. The prescale register divides the system clock by one of several selectable factors equal to non-contiguous powers of two (e.g., by 1, 8, 64 or 1,024) to establish respective prescale time periods (of 1, 8, 64 or 1024 system clocK pulses). One of the several possible prescaling factors is selected by a pair of lines from the system address bus. As a result, the interval timer can be configured with one load operation for an interval within a range which was possible in the prior art only with double the number of data lines and double the length of the countdown register. Chip layout is thus optimized, and the number of control lines needed to access timer functions is reduced, with acceptable loss of flexibility.

Digital device for synchronous data communication

Abstract: An integrated circuit synchronous data adaptor (SSDA) provides a bidirectional interface for synchronous data interchange. Internal control and interface logic including first-in-first-out (FIFO) buffer memory enables simultaneous transmitting and receiving of standard synchronous communication characters to allow data transfer between serial data channels and the parallel bidirectional data bus of a bus organized system such as a microprocessor (MPU) system. Parallel data from the bus system is serially transmitted and received by the SSDA with synchronization character insertion and deletion, fill character insertion and deletion, parity generation and error checking. The functional configuration of the SSDA is programmed via the MPU system data bus during system initialization and can be reconfigured via program control during subsequent system operation. Programmable control registers provide control for variable word lengths, transmit control, receive control, synchronization control, and interrupt control. Status, timing and control lines provide peripheral unit or modem control.

Generator for spelled speech and for speech

Abstract: of the Disclosure A spelled speech or speech generator consists of a central processing unit (CPU), a first memory storing operating program signals for the CPU, a second memory storing signals representative of predetermined portions of phonemes and repetition counts therefor, an address bus interconnecting the CPU and an address input of each memory, an audio output port driving a digital to analog converter for providing an audio output signal, and a data bus interconnecting the input of the audio output port to an output of the second memory. The CPU is actuated to serially address predetermined ones of memory locations, whereby said phoneme-portion signals can each be repeated a number of times designated by said repetition count signals in a sequence and applied to the input of the audio output port to provide a complete phoneme signal. The size of the memory can be minized by storing only a few partial phonemes.

Memory for telecommunications system - has registers forming closed chain of memory modules

Abstract: The memory used in a telecommunications system, for storing data packets etc., has registers (RD) in the form of memory modules (M1 .Mn) connected in series to form a closed chain. Each of the memory modules (M1 .Mn) has a logic access (LA) connected to a data bus line (B1) and a control bus line (B2) which are both connected to a command control unit (C1). The registers (RD) are connected to one another by a circulating memory line (B3), with the data bus line (B1) and the control bus line (B2) forming a closed loop with the command control unit (C1).

Some resource allocation policies in a Multi Associative Processor

Abstract: The Multi Associative Processor is a hypothetical machine composed of eight control units and an arbitrary number of processing elements. Each control unit executes a single-instruction-stream multiple-data-stream program in conjunction with a subset of the dynamically allocatable processing elements. In this machine, the data bus interconnecting control units and processing elements is partitioned in order to decrease the hardware cost of the interconnection. In previous work, the degree of partitioning was investigated, and it was found that the processing element allocation algorithm was very critical to the performance of the system, [5]. In this paper, a basic allocation algorithm is investigated under various job loads, and then the performance is compared to three distinct algorithms that compact processing elements into smaller subsets of the partitions under varying conditions.

Error detecting system of data transmission

Abstract: PURPOSE:False data detecting system of data transmitting system wherein data are transmitted by multiple peripheral stations through common data bus.

Bus control system

Abstract: PURPOSE:To improve the data transfer efficiency by utilizing the difference of transmission data to select a processor of the data transmission side while transmitting data from plural processors. CONSTITUTION:Plural processors 1a, 1b, 1c-1n are connected to one another through corresponding data busses 2a, 2b, 2c-2n and control lines 8 and 9. Each data bus goes to the high level when all of outputted transmission data are in the high level, but the data bus goes to the low level when any of them is in the low level. The data bus is connected to a data reception control part of the corresponding processor and is connected to data transmission control parts of the other processors. Each data transmission control part consists essentially of a demultiplexer 11, a multiplexer 12, and a shift register 13 where transmission data is stored. Processors which detect the difference of bit data stop the data transmission successively, and only one processor completes the transmission of all data bits of transmission data.

Simulating an aerospace multiprocessor

Abstract: The paper describes a simulator which was used to evaluate the architecture of an aerospace multiprocessor. The simulator models interactions among the processors, memories, the central data bus, and a possible 'job stack'. Special features of the simulator are discussed, including the use of explicitly coded and individually distinguishable 'job models' instead of a statistically defined 'job mix' and a specialized Job Model Definition Language to automate the detailed coding of the models. Some results are presented which show that when the simulator was employed in conjunction with queuing theory and Markov-process analysis, more insight into system behavior was obtained than would have been with any one technique alone.

Bus switching unit for electronic computer

Abstract: PURPOSE: To secure an easy common use of an input/output unit given from plural processors by means of one unit of bus switching unit, by providing a priority circuit to the bus switching unit and by holding directly the input/output unit in common COPYRIGHT: (C)1978,JPO&Japio

Bi-Directional Multi-Station Command/Information Bus

Abstract: : The suitability of dielectric waveguide as a transmission medium in data bus applications has been presented in this report The feasibility of the concepts has been demonstrated through a Model 400 Dielectric Waveguide Data Bus System The system operates at millimeter-wave frequencies (22 to 30 GHz) and has two frequency division multiplexed (FDM) data channels, each of which can carry data at rates of up to about 10 Mb/s The system demonstrates multi- channel bi-directional data transfer capabilities over a 100 ft dielectric cable In this report the design features and test results of a tunable bandpass ring coupler are also presented These couplers are used in the Model 400 System for coupling signals to and from the data bus In addition to hardware demonstration of dielectric waveguide systems, their concepts have been used to obtain a data bus configuration for a specific aircraft For this purpose, flight control signals of the YF-16 aircraft were chosen as an illustration The data bus configuration for this aircraft has been presented in a block diagram form It shows that the dielectric waveguide system can fully accommodate all the signal flow requirements

A unified signal processor for tacan navigation sets

Abstract: The unified signal processor (USP) performs the functions of dedicated analog and digital hardware using a timeshared microprocessor which is controlled by a program stored in a read only memory (ROM). The basic advantages are high reliability, low cost and parts count, high flexibility, freedom from drift and adjustments, unlimited precision in signal processing and the USP lends itself ideally to micro-electronic implementation. It has been incorporated in the AN/ARN-119 TACAN navigation set, resulting in improved performance and a two-fold improvement in parts count and reliability as compared to conventional TACAN signal processors. The integrated system has successfully completed flight, qualification and reliability tests. All functions have been verified and the performance equals or exceeds that of conventional microelectronic TACAN sets. The USP extracts and displays range and bearing, performs automatic gain control and self test, and switches antennas. It operates off the TACAN video signal and simultaneously, generates serial digital output signals and analog output signals compatible with synchro indicators. Algorithms for range and bearing acquisition, discrete phase-locked loops, digital filters, automatic gain control, synchro to digital conversion, and data formatting were developed and verified through computer simulations. The microprocessor was designed around the INTEL 8008–1 central processing unit chip. The control program consists of 6000 8-bit instructions, which are stored in 3 read only memories. A common 8-bit tri-state data bus is used to communicate between the central processing unit, the memory and the interfaces. Interfaces necessary to convert between analog signals and digital signals compatible with the data bus form an integral part of the signal processing functions. Portions of these circuits are based on similar circuits used in conventional TACAN sets. Other circuits such as the digital-to-synchro converter, the synchro-to-digital converter, the range and bearing counters, the ID-tone detector, the pulse pair detector, the north burst detector, the encoder and the data rate limiter are new designs.