Showing papers on "Transmission delay published in 1975"

Packet Switching in Radio Channels: Part II--The Hidden Terminal Problem in Carrier Sense Multiple-Access and the Busy-Tone Solution

Abstract: We consider a population of terminals communicating with a central station over a packet-switched multiple-access radio channel. The performance of carrier sense multiple access (CSMA) [1] used as a method for multiplexing these terminals is highly dependent on the ability of each terminal to sense the carrier of any other transmission on the channel. Many situations exist in which some terminals are "hidden" from each other (either because they are out-of-sight or out-of-range). In this paper we show that the existence of hidden terminals significantly degrades the performance of CSMA. Furthermore, we introduce and analyze the busy-tone multiple-access (BTMA) mode as a natural extension of CSMA to eliminate the hidden-terminal problem. Numerical results giving the bandwidth utilization and packet delays are shown, illustrating that BTMA with hidden terminals performs almost as well as CSMA without hidden terminals.

ALOHA packet broadcasting: a retrospect

Abstract: Packet broadcasting is a technique whereby data is sent from one node in a net to another by attaching address information to the data to form a packet---typically from 30 to 1000 bits in length. The packet is then broadcast over a communication channel which is shared by a large number of nodes in the net; as the packet is received by these nodes the address is scanned and the packet is accepted by the proper addressee (or addressees) and ignored by the others. The physical communication channel employed by a packet broadcasting net can be a ground based radio channel, a satellite transponder or a cable.

Digital data communications system packet switch

Abstract: A data communications system designed to facilitate communications between digital computers typically routes fixed-length segments of data, called packets, through minicomputer packet switches located intermediate the digital computers. To mitigate the need for expensive minicomputer arrangements as the intermediate processor, the minicomputers are replaced by a low-cost, high-throughput, modular packet switch having an efficient control memory-queue control arrangement for moving a packet from one time slot to another as well as modifying the packet header as the packet is routed through the communications system.

Performance of Hybrid Error Control Schemes of Satellite Channels

Abstract: The effectiveness of hybrid error control schemes involving forward error correction (FEC) and automatic repeat request (ARQ) is examined for satellite channels. The principal features of the channel are: large round-trip transmission delay due to the satellite link, and burst errors introduced by the terrestrial links that connect the users to the satellite link. The performance is estimated for two channels described by Fritchman's simple partitioned finite-state Markov model, and is compared to that obtainable if the channel is considered as a binary symmetric channel of the same bit error probability. Results show that the hybrid schemes offer substantial improvement over ARQ and FEC, and that an optimum exists for the number of errors corrected to obtain maximum throughput efficiency.

Programmable variable length high speed digital delay line

Abstract: A variable length, digital delay line apparatus utilizing a set of progressively increasing delay devices in conjunction with a set of digitally selectable switching units to vary the delay times over a predetermined delay range.

Packet switching: the experimental packet switched service

Abstract: Manufacture and use of a therapeutic composition which provides for healing of open wounds on animals such as horses while avoiding the development of proud flesh and while acting as a fly repellent and avoiding and curing bacterial infection.

High speed serial data synchronization scheme

Abstract: A serial-to-parallel data conversion and synchronization scheme in which alurality of active logic elements are utilized as delay lines. Each of the delay lines introduces a delay equal to the period of one data bit and one additional delay line introduces a delay equal to one half the period of a data bit. The input of the first delay line is connected to the data input of a first flip-flop and the outputs of each of the plurality of delay lines are each connected to the data input of a flip-flop. The output of the additional delay line is connected to the clock inputs of each of the flip-flops whereby the serial data word is converted to a parallel data word and the conversion is internally clocked by the delay lines themselves.

Information signal transmission system for bucket communication

Abstract: PURPOSE:To increase transmission velocity for communication network, by reducing apparent transmission delay for bucket signal processing of reception unit.

The razorback CCD: A high-performance parallel input delay line architecture

Abstract: An analog CCD delay line with multiple input taps which can be used singly to provide a selectable bit delay, or in parallel to perform delay-sum and multiplexing signal operations, will be covered. These taps are realized along the delay line with high transfer efficiency and large bandwidth.

A High Throughput Packet-Switched Network Technique Without Message Reassembly

Abstract: A new packet-switching network technique is described which, while utilizing certain aspects of the ARPANET technology, introduces a substantially different technique for handling traffic which is longer than a single packet in length. The technique is keyed to a common-user network environment, where a wide variety of subscriber types, ranging from computers to simple terminals, are to be serviced. Subscribers in most cases would be remotely located from the network switching nodes. By splitting the buffering between the originating and destination nodes and by essentially eliminating the segment reassembly process, substantial reductions in on-line buffering can be achieved, while still maintaining short response times for interactive messages and large bandwidths for long data exchanges. In this paper we describe the network operational concepts and traffic flow for various subscriber types, show specific examples and timing diagrams for message flows, and present a comparative analysis of the buffer sizing, throughput, and delay for this new technique compared to the well-known ARPANET technique of packet switching.

Study of overheads in packet-switched data networks

Abstract: An analytical formulation for determining the optimum packet size is presented. The mathematical model developed takes into consideration the message statistics, acknowledgment delays, channel-error characteristics, delays due to retransmission, packet header and the overheads due to blank padding of last packet etc. Network operational overheads have been considered to be functions of packet size. The system analysed is a half-duplex network operating in a stop-and-wait strategy for error detection and correction. The theoretical formulations lead to a 3rd-order algebraic equation having one and only one positive real root - which signifies the optimum packet size. Furthermore, these studies indicate that a packet size can be determined that minimises the network operational overheads; while the overheads due to blank padding increase more or less linearly with packet size.