Showing papers on "Voltage-controlled oscillator published in 1983"

Wide range clock recovery circuit

Abstract: A wide range, variable rate clock recovery circuit for NRZ data is provided having a PLL and a frequency synthesizer which share control of a common VCO in single loop realization. Narrow PLL bandwidths and short acquisition time may be achieved employing the frequency synthesizer to initially control the VCO to produce an estimate of the data frequency which is accurate to within the bandwidth of the PLL. Once this VCO frequency is attained, the PLL disables the frequency synthesizer control of the VCO and provides fine tuning control of the VCO output frequency itself. Single loop realization is achieved with a wide range VCO which includes a narrow range VCO, a frequency divider, and an auto-ranging circuit.

PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction

Abstract: A phase-locked loop frequency synthesizer apparatus for providing an output signal whose frequency jumps from one value to another, at regular intervals of time. Coarse tuning circuitry couples a prescribed signal to the apparatus' voltage-controlled oscillator (VCO), to drive the VCO immediately to the correct frequency each time a new frequency is selected, thereby substantially reducing the apparatus' settling time. In addition, adaptive coarse tuning circuitry continuously updates the values of stored coarse tuning information for each possible frequency, to correct for any drifts in the VCO's voltage/frequency characteristic. A VCO gain normalizer circuit amplifies the error signal coupled to the VCO by an amount that varies with the selected frequency, so as to correct for any non-uniformities in the apparatus' various elements, particularly the VCO, and to thereby provide a uniform loop gain.

Multifrequency microwave source

Abstract: A frequency-agile source of microwave frequency signals is shown to include: a voltage-controlled oscillator operating within a band of microwave frequencies; a crystal-controlled oscillator operating at a frequency lower than the band of microwave frequencies and producing harmonics within such band; a phase detector having samples of the signals out of the crystal-controlled oscillator and the voltage-controlled oscillator applied as input signals; and a shaping amplifier receiving the output signal of the phase detector to provide a control signal related to the phase difference between the signal out of the voltage-controlled oscillator and the harmonic of the crystal-controlled oscillator nearest to the frequency of the voltage-controlled oscillator.

Disciplined oscillator system with frequency control and accumulated time control

Abstract: A disciplined oscillator system having a standard oscillator which is automatically corrected for both frequency errors and time error accumulation to a constant frequency signal which is derived from the WWVB carrier frequency and the WWVB TIME CODE to maintain overall frequency accuracy within one part in 10 9 notwithstanding oscillator aging and in spite of jitter and distortion due to propagation delays and noise which may cause loss of, or time jitter in, the WWVB signals. Frequency errors are detected through the use of a counter (24) having a measurement accuracy greater than one part in 10 10 . An error detector (26) derives correction signals by averaging a plurality of frequency variances obtained in successive measurement cycles. Timing errors are corrected by dividers (34, 40) controlled by a timing discriminator (36) which responds to timing variance between signals from the standard oscillator and from the WWVB reference which are phase locked to those TIME CODE signals which are substantially free of noise and jitter. The timing correction is inhibited after the standard oscillator is corrected. Frequency correction is applied continuously.

Inherent Overload Protection for the Series Resonant Converter

Abstract: The overload characteristics of the full bridge series resonant power converter are considered. This includes analyses of the two most common control methods presently in use. The first of these uses a current zero crossing detector to synchronize the control signals and is referred to as the ? controller. The second is driven by a voltage controlled oscillator and is referred to as the ? controller. It is shown that the ? controller has certain reliability advantages in that it can be designed with inherent short circuit protection. Experimental results are included for an 86 kHz converter using power metal-oxide-semiconductor field-effect transistors (MOSFETs).

Interruptable voltage-controlled oscillator and phase-locked loop using same

Abstract: The fall-time of an ECL gate is precisely controlled using a fixed capacitor, which is connected between the positive supply voltage and the ECL gate output terminal, and a variable current source connected between ground and the ECL gate output terminal. A time-delay circuit is obtained by controlling the variable current source with an error voltage of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates with controlled fall-times in a ring oscillator configuration. Addition of a non-inverting input to one ECL gate makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided by phase-locking the output signal of a first phase-locked loop to a system reference signal to generate a first-loop control voltage. A second phase-locked loop is phase-locked to the received signal with a second-loop control voltage. In addition, the second phase-locked loop is also frequency-locked to the system reference signal by the first-loop control voltage. This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal.

Electronic high frequency controlled device for operating gas discharge lamps

Abstract: A high frequency electronic ballast which comprises a variable frequency oscillator (1) having its frequency controlled by inputs (10 to 15). The oscillator (1) providing complementary outputs (16, 17) which controls an inverter (4) via a driver circuit (3). The inverter output is a source for a transformer or choke (5) which directly drives a gas discharge lamp (6). In this way the frequency of operation and hence the illumination of the lamp (6) can be changed by changing the driver (3) frequency by direct control (10 to 15) of the oscillator (1) and the lamp voltage is maintained substantially constant while reducing its current flow.

Method and apparatus for eliminating interference due to spurious signals generated in synthesized receivers

Abstract: A synthesizer radio frequency (RF) signal receiver (FIG. 1) for single sideband radios is described that can eliminate interference due to internally generated spurious signals, commonly referred to as "whistler spurs". The unique receiver includes first and second mixers (102 and 106), which are intercoupled by a 75 mHz crystal filter (104) having a 20 kHz passband, and which are each coupled to signals from voltage controlled oscillators (120 and 140). The first IF frequency provided by the first mixer (102) varies about 75 mHz, and the second IF frequency provided by the second mixer (106) is fixed at 11.4 mHz. The second mixer (106) is coupled to 11.4 mHz stages (108) which have a 2.7 kHz passband. The 11.4 mHz stages (108) are followed by another mixer (110) and audio stages (112) for demodulating audio signals from the received RF signal, which are then applied to a speaker (114). The frequency of the VCO (120) coupled to the first mixer (102) can be varied by changing the divisor N of a programmable divider (123), and the frequency of the VCO (140) coupled to the second mixer (106) likewise can be varied by changing the divisor M of a programmable divider (133). When interference due to a whistler spur is present, activation of an IF pushbutton (160) enables a microcomputer (170), which changes divisors N and M for varying the frequencies of the two VCO's (120 and 140) by a multiple of 3.2 kHz, which in turn shifts the first IF frequency by 3.2 kHz. The frequency change also shifts the whistler spur outside of the 2.7 kHz passband of the 11.4 mHz stages (108) and greatly attenuates it. If the whistler spur is not sufficiently attenuated, the IF pushbutton (160) can be activated a second time.

Induction loop vehicle detector

Abstract: An induction loop vehicle detector comprises an oscillator circuit having a plurality of capacitors switchable in circuit with a road loop under the control of a microcomputer to determine the oscillator frequency. The microcomputer monitors the oscillator frequency and controls the switching of the capacitors to periodically return the frequency to a predetermined value. A counter counts a predetermined number of oscillator cycles and gates of h.f. clock into a second counter whereby the count of the counter represents the oscillator period. A "vehicle detected" output is given when the monitored frequency alters by more than a predetermined amount, representing a decrease in the inductance of the loop. On detecting an increase in the inductance above a predetermined threshold the detector is inhibited for a predetermined time, e.g. about 1 second, to avoid errors caused by magnetic effects.

Apparatus for and method of compensating for variations due to aging

Abstract: Variations, due to aging, of resonant frequency characteristics of electromechanical resonators are compensated by an oscillator including the resonantor. An indication of the amount of time that the oscillator is operating addresses a table of values indicative of the manner in which the oscillator changes frequency as the resonator ages. From the table of values a signal having a value indicative of a correction factor for the resonator aging is derived. The frequency of the oscillator is controlled in response to the value of the correction factor. The table of values is stored in a re-programmable memory. The values stored in the memory are corrected by comparing the oscillator frequency with a standard frequency.

RF Local oscillator with low phase noise

Abstract: An RF local oscillator, particularly useful in connection with phase shift key modulation in satellite communications systems, provides a low phase noise signal by use of a phase locked loop having a phase stable oscillator to provide frequency conversion of a frequency synthesizer output signal.

Digital automatic frequency control with tracking

Abstract: A microprocessor controlled phase locked loop tuning system is disclosed which uses a single AFC detector whose threshold is controlled by the microprocessor. The system comprises a microprocessor (10) which provides frequency data to the PLL (11), and this data controls a programmable frequency divider in the PLL which determines the nominal frequency of a VCO (131) in the tuner (13). An AFC detector (141) in the intermediate frequency section (14) provides an AFC voltage output to the single comparator (15). The comparator produces a logic "0" or a logic "1" output to the microprocessor depending on whether the output from the AFC detector is above or below a predetermined threshold. The microprocessor is first operated in a frequency search mode to increase or decrease the frequency of the VCO in predetermined frequency increments depending on the logic state of the output of the comparator (15). During this mode of operation, the microprocessor may be programmed to respond to a change of state of the output of the detector by causing the frequency of the VCO change in the opposite direction to produce a successive predetermined number of detector output state changes and also to cause the VCO frequency changes to be made in smaller increments. After a predetermined number of detector output state changes have been detected, the microprocessor is then operated in a track mode during which time the microprocessor periodically and temporarily changes the predetermined threshold of the detector (15) alternately up and down by supplying pulses to the input of the detector. In this way a "window" is generated to track the tuning frequency.

Frequency synthesis tuning control system for a double-conversion tuner

Abstract: The tuning control system of a double-conversion tuner includes a phase locked loop type of frequency synthesizer for controlling the frequency of a controllable oscillator comprising the first local oscillator of the double-conversion tuner according to the frequency deviation of the difference between the frequencies of the first and second local oscillators from a reference frequency in order to compensate for the drift of either one of the local oscillators. An up/down counter which counts in one sense in response to the first local oscillator signal and in the other sense in response to the other local oscillator signal is used to generate the frequency difference signal. Because the frequency of the first local oscillator is always greater from the frequency of the second local oscillator the up/down counter can be implemented in the form of a simple pulse swallower.

Enhanced frequency modulation in cleaved‐coupled‐cavity semiconductor lasers with reduced spurious intensity modulation

Abstract: We have observed enhanced analog frequency modulation in a cleaved‐coupled‐cavity (C3) laser. One diode is dc biased above threshold to produce the desired output power and the other diode, the modulator, is biased below threshold with a dc current and a small modulating current superimposed to achieve analog frequency modulation of the output beam. Comparing with direct analog frequency modulation of a conventional semiconductor laser, the C3 laser has allowed us to obtain significantly larger frequency deviation with negligible spurious intensity modulation. Further, the present frequency modulation response is also much more uniform with respect to modulation frequency. In addition, this scheme is applicable to C3 lasers formed from all laser structures.

Timing extraction circuit

Abstract: A timing extraction circuit includes a phase comparator, a charge pump circuit, a filter circuit and a voltage controlled oscillator, these components constituting a phase-locked loop. The phase comparator compares the phases of a digital data signal and a timing signal and supplies first and second difference signals to the charge pump circuit. The charge pump circuit detects a phase error corresponding to the difference between the integrals of the first and second difference signals. The filter circuit supplies a control signal corresponding to the phase error to the voltage controlled oscillator. The voltage controlled oscillator generates the timing signal having a period corresponding to the control signal.

Decision-directed, automatic frequency control technique for non-coherently demodulated M-ARY frequency shift keying

Abstract: A data receiver apparatus for recovering digital data signals from an M-ARY FSK modulated signal incorporates a dedicated linear discriminator, downstream of the data recovery process, in the carrier tracking loop. Because the signal modulation components are removed prior to tracking, only frequency error remains, which is employed by the linear discriminator for steering a VCO in the frequency tracking loop. This results in a closed loop step response that rapidly converges to a stable level, and a linear frequency estimation characteristic.

Frequency synthesizer with improved priority channel switching

Abstract: A frequency synthesizer is provided including a reference frequency generator coupled to one input of a phase detector. The output of the phase detector is coupled via a pair of alternatingly connected filters through a voltage controlled oscillator and a divider circuit to the remaining input of the phase detector to form a phase locked loop. The first filter of the pair is designated for operation on a main channel frequency while the remaining filter is designated for operation on a priority channel frequency. The capacitive elements of each respective filter remain fully charged up for operation on their respective frequencies and thus when such filters are alternately switched between to change frequency from the main channel to the priority channel, the capacitive elements need not be charged to new levels to accommodate such frequency change. Thus, switching between a main channel and a priority channel is accomplished in a minimal amount of time with a significant reduction in frequency synthesizer energy requirements.

Digital clocking and detection system for a digital storage system

Abstract: A data clocking and detection system for a digital data storage system includes a common controlled oscillator (16) for the multiple tracks. A phase detector (18) for each track includes a counter and decoding circuitry producing outputs representing the time occurrence of transitions in the data with respect to bit cells defined by multiple clock pulses for each bit cell. Phase errors are used to control the frequency of the VCO, and large phase errors are used to add or subtract a count from the phase counter in each phase detector.

Prepositioning circuit for phase lock loop

Abstract: Prepositioning of a phase lock loop by charging or discharging the loop filter capacitor to a voltage close to the desired VCO control voltage is accomplished rapidly by the addition of a current pump The current pump, responsive to a tuning voltage corresponding to the VCO control voltage provides a pulse of high rate current to charge or discharge the capacitor The current pulse, which is of sufficient length to ensure that the capacitor achieves the desired voltage, swamps out the contribution of the loop charge pump which is responsive to the loop phase detector When disabled, the current pump appears as a virtual open circuit to the loop capacitor, so that no current leakage occurs through the current pump

Digital phase lock loop system

Abstract: A macro phase detector responds to large phase deviation between a locally generated signal and a reference signal for actuating a successive frequency approximation register to effect major count alteration in a counter for controlling a digital-to-analog converter and, in turn, a voltage controlled oscillator. Small phase error is detected by a phase detector, averaged, and employed to alter the count in the counter for introducing sensitive frequency adjustment. A second counter is clocked by the phase detector at one half the rate of the first counter and is used to update the first counter each time the phase difference reverses polarity. Loss of reference signal activates a detector for freezing the count in the counter to maintain frequency and phase within the accuracy of the controlled oscillator.

Random sequence generators

Abstract: A pseudo-random sequence generator has two oscillators, the first of which controls the rate of stepping through the pseudo-random sequence and the second of which controls selection of the sequence and the inverse of the sequence. By replacing the second oscillator with a voltage controlled oscillator and deriving the control voltage from a decaying Integration of at least one output of the random sequence generator (or another pseudo-random sequence generator) a near-true digital noise is produced.

Watthour test circuitry

Abstract: The present invention accepts accurately generated pulses, having a frequency of K pulses per second, from a suitable source of such pulses, and uses those pulses to phase correct the operation of a phase lock loop voltage controlled oscillator, which is designed to run at a frequency of N times K pulses per second. The output pulses from the voltage controlled oscillator are passed along a bifurcated path. Along one leg of said bifurcated path, the pulses are directed to a counter where they are divided down to provide an output signal at the rate of NK/P pulses per second and in the preferred embodiment, P equals N. The pulses from the counter are fed at the NK/P rate back to a phase comparator which provides an error voltage at the voltage controlled oscillator for each pulse. The present invention further includes logic circuitry which is connected to the second of said bifurcated path legs to receive the pulses which are at the NK pulse per second rate and this logic circuitry is further connected to the output of the counter to receive pulses therefrom at the NK/P pulse per second rate. The logic circuitry is designed to be able to provide pulses at either the NK rate, or at the NK/P rate depending upon how the pulses are to be employed.

Data clocking circuitry

Abstract: Clocking circuitry for providing clocking signals in accordance with a preprogrammed sequence of rates. An addressable memory (11) is included having data defining such rates with a voltage controlled oscillator (VCO) (8) controlled via data from the addressable memory (11). An address producing means is controlled by the clocking signals of the VCO (8) to provide an address signal for the memory in response to each clocking signal. The clocking circuitry is used with a moving mirror (3) for a laser printer apparatus, the mirror (3) having a known repetitive move­ ment which is used in establishing the preprogramed sequence of rates.

Frequency control device to synchronise an oscillator with an external signal of very accurate mean frequency but having a high jitter

Abstract: A frequency control device includes an analog phase locked loop, which operates on initial switch-on, and a digital frequency locked loop which takes over from the analog loop when it is locked to control the same voltage controlled oscillator (OCT) so as to ensure faster locking. Control of the oscillator successively by the two loops uses a switching circuit (ANA) with two inputs, one for the analog loop (OCT, C???, F) and one for the digital loop (OCT CF, P). This switching circuit includes a sampler- coder (EC), an up-down counter (CD), a register (RE), and a D/A connector (CNA). The sampler-coder input is the one for the phase loop, and the inputs for the counter are those for the frequency loop. The reference signal for both control loops is the external signal (E). In the phase loop configuration the sampler-coder, up- down counter and register are driven by a high frequency signal (T1) of about 1 MHz. In the frequency loop configuration the sampler-coder is ineffective and a lower frequency signal (To) of about 1 Hz drives the register. The device is useful in digital (PCM) telephone exchanges.

Master clock generator for telecommunications system

Abstract: A very stable master clock for satellites is disclosed. Time division multiple access techniques are used to permit individual earth stations to be received by the satellite in separate non-overlapping time slots. The satellite switched time division multiple access systems are compatible with the onboard satellite clock by providing a comparator control logic loop to produce a signal representing the phase difference between the onboard oscillator clock and the earth station. Control signals are generated to correct the voltage controlled oscillator onboard the satellite.

Demodulation circuit for a digitized chrominance signal having a sampling signal oscillator coupled to a chrominance signal oscillator

Abstract: In a digital demodulation circuit for a chrominance signal of a color television signal having a first digital oscillator (35) for producing reference signals and a phase control loop (29, 17, 19, 49, 43) therefor, there is added in the phase control loop a signal combination (at 56) which is obtained from a phase control loop (67, 63, 59) of a second digital oscillator (77). This second digital oscillator derives the sampling frequency for sampling the chrominance signal from a signal source (83) of a constant frequency and couples this sampling frequency to the horizontal deflection frequency. By the addition in the phase control loop of the first oscillator, variations in the horizontal deflection frequency cannot lead to the undesired phenomenon of the first digital oscillator being pulled to a side-band frequency of the color subcarrier wave.

Surface acoustic‐wave device for measuring high voltages

Abstract: A surface acoustic‐wave (SAW) device for measuring high voltages is described. The device consists of two SAW oscillators fabricated on a 128° rotated Y‐cut LiNbO3 substrate. The voltage to be measured is applied to one of the oscillators while the other oscillator acts as the reference oscillator for temperature compensation purposes. The frequency of the perturbed oscillator varies linearly with the applied voltage. An oscillator fabricated on a 0.5‐mm‐thick substrate can withstand greater than 9 kV of voltage giving a fractional frequency deviation greater than 1630 parts per million. Attractive features of this technique include: (1) direct measurement of high voltages without the need for resistive or capacitive voltage dividers, (2) very high input resistance, (3) direct conversion of voltage to frequency, and (4) resolution better than 0.01% of full scale. This paper will discuss the basic operation and present experimental data on the performance of the device. A technique for obtaining improved t...

Fm receiver including a frequency-locked loop

Abstract: FM-receiver including a frequency-locked loop (2-14), which loop includes, successively connected, a voltage controlled oscillator (8), a mixer circuit (2) connected to an aerial input, an IF-portion comprising an IF-filter (9), an FM-detector (4), a loop filter arrangement (5) and a loop amplifier (6) for adjusting the transfer characteristic of the frequency locked loop (2-14), which loop amplifier (6) is connected to a control input of the voltage-controlled oscillator (8) for a feedback of the modulation signal of the received FM-signal, which loop filter arrangement (5) comprises a first low-pass filter (14), the FM-receiver being realizable in integrated circuit form and suitable for processing FM-stereo signals. So as to ensure that for the processing of FM-stereo signals the receiver is at least comparable to conventional FM-stereo receivers as regards selectivity, harmonic distortion and stability which conventional FM-stereo receivers are not realizable in integrated circuit form, the stereo sum and the stereo difference signal being selectively and separately fedback via two simple, comparatively weakly selective parallel-arranged filter circuits (14; 18).

Method and circuit for frequency and phase locking a local oscillator for television

Abstract: A conventional phase locking loop for locking a local oscillator in phase and frequency to a color burst signal in a television system requires a highly stable (i.e. crystal controlled) oscillator whose free running frequency must be individually adjusted to be as close as possible to the desired frequency. The present invention enables such adjustment to take place automatically in operation rather than as a separate manufacturing step. The output from the oscillator is compared in phase with the color burst signal to which it is to be locked. The output from the phase comparator is applied to one input of a differential amplifier whose output constitutes an error signal for application to a frequency controlling input of the oscillator. The error signal is also applied to a threshold control circuit which causes an up/down counter to count up or down when the error signal lies outside a predetermined range. The counter total is converted to analog form and is applied to the control input in addition to the error signal.

Device for the automatic linearization of the control signal-frequency characteristic of a frequency-modulated variable frequency oscillator

Abstract: A phase lock loop having an instruction input to which is applied the output signal of the frequency-modulated variable frequency oscillator. The pass band of the loop is regulated in order to obtain at its output, a frequency-filtered signal corresponding to the frequency-modulated signal applied to the instruction input. A phase demodulator having inputs coupled to the instruction input of the loop and to the output of the loop supplies a signal corresponding to the modulation index of the signal supplied by the oscillator. This signal is compared with a reference signal by a comparator circuit, which supplies a control signal to means for adjusting the amplitude of the modulating signal applied to the input of the oscillator, in order to permanently adjust the modulation index of the frequency-modulated signal, produced at the output of the oscillator, to the value of the desired modulation index corresponding to the reference signal.