Low-power cryogenic low-noise amplifiers (LNAs) are desired to ease the cooling requirements of ultra-sensitive cryogenically cooled instrumentation. In this paper, the tradeoff between power and noise performance in silicon–germanium LNAs is explored to study the possibility of operating these devices from low supply voltages. A new small-signal heterojunction bipolar transistor noise model applicable to both the forward-active and saturation regimes is developed from first principles. Experimental measurements of a device across a wide range of temperatures are then presented and the dependence of the noise parameters on collector–emitter voltage is described. This paper concludes with the demonstration of a high-gain 1.8–3.6-GHz cryogenic LNA achieving a noise temperature of 3.4–5 K while consuming just ${\hbox{290}}~\mu{\hbox{W}}$ when operating at 15-K physical temperature.

Ultra-Low-Power Cryogenic SiGe Low-Noise Amplifiers: Theory and Demonstration

We study crosstalk and crosstalk corrections in coplanar-waveguide vector-network-analyzer calibrations We show that while crosstalk corrections can improve measurement accuracy, the effectiveness of the corrections depends on a number of factors, including the length of the access lines, transverse dimensions, the separation between the crosstalk standards, and the substrate configuration

Crosstalk Corrections for Coplanar-Waveguide Scattering-Parameter Calibrations

This paper presents a quantitative comparison of the reference multiline TRL and LRM+ for a customized set of standards in a CMOS process using IBM's 013 mum technology This comparison was undertaken for the first time and covered a frequency range from 1 to 110 GHz It was demonstrated that the accuracy of the on-wafer multiline TRL and LRM+ calibration were in very good agreement Both methods outperform the conventional off-wafer calibration with the DUT contact pad parasitics de-embedded

Comparison of on-wafer multiline TRL and LRM+ calibrations for RF CMOS applications

We report record RF FET performance in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm and analyze factors contributing to that performance The effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX A peak fT of 330 GHz is measured in a fully-wired 65-nm NFET A complete de-embedding method to accurately determine RF characteristics of the intrinsic 90-nm SOI NFET results in a peak fT of 290 GHz and an fMAX of 450 GHz

Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies

This paper presents a general 4-port algorithm that can remove on-wafer parasitics from on-wafer measurements after impedance standard substrate (ISS) calibration of system errors, or remove both system errors and on-wafer parasitics in a single step without ISS calibration. On-wafer standards are fabricated on a 0.13 RF CMOS process, and experimental data are measured from 2 to 110 GHz using an HP 8510XF system. The impact of nonideal on-wafer load standards is examined using the deembedded transistor-parameters and the extracted small signal parameters. The errors remaining after the traditional open-short deembedding are numerically evaluated, which become significant above 50 GHz. The solved 4-port network for on-wafer parasitics is indeed reciprocal despite the assumptions of ideal OPEN and SHORT, thus allowing a mathematically simpler reciprocal 4-port solution. The general 4-port solution can also be directly applied to the measured raw S-parameters to remove both system errors and on-wafer parasitics in a single step. Single-step calibration leads to reasonably accurate transistor -parameters, despite the less accurate on-wafer standards compared to precision ISS standards.

A General 4-Port Solution for 110 GHz On-Wafer Transistor Measurements With or Without Impedance Standard Substrate (ISS) Calibration

The impedance errors remaining after applying the industry standard "open-short," a "pad-open-short," and a "open-short-load" deembedding scheme on a 0.43-nH 20-GHz high-Q single-loop inductor test structure are investigated using real S-parameter data taken up to 50 GHz. Since the latter two deembedding schemes both correct for all parasitic elements of the test structures, they are, at least in principle, error free. The accuracy of the "open-short-load" deembedding scheme, however, critically depends on how well the reactive part of the load resistance is accounted for. This issue makes the more simple "pad-open-short" deembedding scheme an attractive choice because the required split between external and internal capacitances is easy to make, either based on process and layout information or from measurements done on a "pad" dummy structure

https://www.bioee.ee.columbia.edu/courses/upload/Bibliography/tiemeijer2005.pdf?origin=publication_detail

A.B.M. Jansman

Papers

Comparison of the "pad-open-short" and "open-short-load" deembedding techniques for accurate on-wafer RF characterization of high-quality passives