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Journal ArticleDOI

Comparison of the "pad-open-short" and "open-short-load" deembedding techniques for accurate on-wafer RF characterization of high-quality passives

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TLDR
In this paper, the impedance errors remaining after applying the industry standard "open short," a "pad-open-short," and a "Open Shortload" deembedding scheme on a 0.43-nH 20-GHz high-Q single-loop inductor test structure are investigated using real S-parameter data taken up to 50 GHz.
Abstract
The impedance errors remaining after applying the industry standard "open-short," a "pad-open-short," and a "open-short-load" deembedding scheme on a 0.43-nH 20-GHz high-Q single-loop inductor test structure are investigated using real S-parameter data taken up to 50 GHz. Since the latter two deembedding schemes both correct for all parasitic elements of the test structures, they are, at least in principle, error free. The accuracy of the "open-short-load" deembedding scheme, however, critically depends on how well the reactive part of the load resistance is accounted for. This issue makes the more simple "pad-open-short" deembedding scheme an attractive choice because the required split between external and internal capacitances is easy to make, either based on process and layout information or from measurements done on a "pad" dummy structure

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Citations
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Journal ArticleDOI

Ultra-Low-Power Cryogenic SiGe Low-Noise Amplifiers: Theory and Demonstration

TL;DR: In this article, the tradeoff between power and noise performance in silicon-germanium LNAs is explored to study the possibility of operating these devices from low supply voltages.
Journal ArticleDOI

Crosstalk Corrections for Coplanar-Waveguide Scattering-Parameter Calibrations

TL;DR: In this paper, the authors study the effect of crosstalk corrections in coplanar-waveguide vector-network-analyzer calibrations and show that the effectiveness of the corrections depends on a number of factors, including the length of the access lines, transverse dimensions, the separation between the crossstalk standards, and the substrate configuration.
Proceedings ArticleDOI

Comparison of on-wafer multiline TRL and LRM+ calibrations for RF CMOS applications

TL;DR: In this article, the authors present a quantitative comparison of the reference multiline TRL and LRM+ for a customized set of standards in a CMOS process using IBM's 013 mum technology.
Proceedings ArticleDOI

Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies

TL;DR: In this article, the effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX, in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm.
Journal ArticleDOI

A General 4-Port Solution for 110 GHz On-Wafer Transistor Measurements With or Without Impedance Standard Substrate (ISS) Calibration

TL;DR: In this article, a general 4-port algorithm was proposed to remove parasitics from on-wafer measurements after impedance standard substrate (ISS) calibration of system errors, or remove both system errors and onwafer parasitICS in a single step without ISS calibration.
References
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Proceedings ArticleDOI

An improved de-embedding technique for on-wafer high-frequency characterization

TL;DR: In this paper, an improved correction procedure for on-wafer S-parameter measurements has been developed and implemented, which takes the effects of series parasitics into account in a simple, straightforward way.
Journal ArticleDOI

An efficient method for computer aided noise analysis of linear amplifier networks

TL;DR: In this paper, a two-port noise analysis based on correlation matrices is presented. But the correlation matrix concept holds two main advantages over other methods of noise analysis: it can be treated without any loss of efficiency and information concerning minimum noise figure and noise matching conditions is obtained.
Journal ArticleDOI

A three-step method for the de-embedding of high-frequency S-parameter measurements

TL;DR: In this paper, the authors proposed a general method of deembedding S-parameter measurements of the device under test (DUT) for which typical parasitics associated with probe pads and interconnect-metal lines can be deembedded from the measurement.
Journal ArticleDOI

Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures

TL;DR: In this paper, an improved three-step de-embedding method is proposed to subtract the influence of parasitics in the test-structure stemming from the contact pads, the metal interconnections and the silicon substrate.
Journal ArticleDOI

A four-step method for de-embedding gigahertz on-wafer CMOS measurements

TL;DR: In this article, a de-embedding method is proposed for accurate on-wafer device measurements in the gigahertz range, addressing issues of substrate coupling and contact effects and is therefore suitable for measurements with lossy technologies such as CMOS.
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