ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

We analyze, from a theoretical point of view, a novel silicon optical amplitude-phase modulator integrated into a SOI (silicon on insulator) optical waveguide and based on a three terminal electronic structure which gives rise to definite advantages in comparison with a classical p-i-n diode based modulator. The proposed device utilizes the free carrier dispersion effect to produce the desired refractive index and absorption coefficient variations. The MEDICI two-dimensional (2-D) semiconductor device simulator has been used to analyze the electrical operation, with reference to the free carrier concentration injected into the optical channel, its uniformity and the required current density and electrical power. The optical investigation was carried out by means of FDM (finite difference method), EIM (effective index method), and BPM (beam propagation method) tools, giving rise to a complete evaluation of the properties of our device. We report the results for both the amplitude and phase modulators, paying attention to the static and the dynamic behavior. In particular, an amplitude modulation of 20%, with an injection power of about 126 mW, and a switching time of 5.6 ns can be achieved theoretically, Furthermore, as a phase modulator, the device exhibits a very high figure of merit, predicting an induced phase shift per volt per millimeter of about 215/spl deg/, for a injection power of about 43 mW, and a switching time shorter than 3.5 ns.

Silicon electro-optic modulator based on a three terminal device integrated in a low-loss single-mode SOI waveguide

A detailed study of the on state of amorphous threshold switches has been performed. Transient and steady‐state I‐V characteristics have been investigated as functions of film thickness, pore size, and electrode material. Velocity saturation effects in amorphous/crystalline Si heterojunctions and threshold recovery curves were also studied. It is found that the on‐state resistivity is approximately 0.08 Ω cm, independent of electrode material. The on state is that of a semiconductor whose electronic band structure and carrier mobility are essentially unchanged from the off state, but in which a concentration of about 7×1018 free electron/cm3 produces the high conductivity observed. The decay of the on state is due to a combination of diffusion of the free carriers out of the filament, together with direct carrier recombination. A major result of this work is the determination of the size of the conducting filament as a function of operating current. As expected, the current density in the filament is esse...

On state of amorphous threshold switches

A systematic method is given for generating negative-resistance circuits made of 2 transistors and linear positive resistors only. The 2 transistors may be bioolar ( n-p-n or p-n-p ), JFET ( n -channel or p-channel), MOSFET ( n -channel or p -channel), or their combinations. Since the circuits do not require an internal power supply, they are passive and can be integrated as a two-terminal device in monolithic form. Two algorithms are given for generating a negative-resistance device which exhibits either a type- N \upsilon - i characteristic similar to that of a tunnel diode, or a type- S \upsilon -i characteristic similar to that of a four-layered p-n-p-n diode. Hundreds of new and potentially useful negative resistance devices have been discovered. A selected catalog of many such prototype negative-resistance devices is included for future applications.

Bipolar - JFET - MOSFET negative resistance devices

Investigates the effects of self-heating on the high current I-V characteristics of semiconductor structures using a fully coupled electrothermal device simulator. It is shown that the breakdown in both resistors and diodes is caused by conductivity modulation due to minority carrier generation. In isothermal simulations with T=300 K, avalanche generation is the source of minority carriers. In simulations with self-heating, both avalanche and thermal generation of minority carriers can contribute to the breakdown mechanism. The voltage and current at breakdown are dependent on the structure of the device and the doping concentration in the region with lower doping. For all structures, except highly doped resistors with poor heating sinking at the contacts, the temperature at thermal breakdown ranged from 1.25T/sub i/ to 3T/sub i/, where T/sub i/ is the temperature at which the semiconductor goes intrinsic. Hence, it is found that T=T/sub i/ is not a general condition for thermal (or second) breakdown. From these studies, an improved condition for thermal breakdown is proposed. >

Self-heating effects in basic semiconductor structures

“Bipolar operation”, namely forward-basing the gate-source diode of a JFET, has been proposed in the literature as a means to reduce the on-state resistance of such devices. In this paper, the physics of bipolar operation of power JFET's is analysed in detail and closed-form solutions of its output characteristics are derived as a function of the device geometry and of physical parameters of the semiconductor. From that model, it turns out that the low value of the saturation voltage originates from the existence of an high-density electron-hole plasma that fills the space between source and drain. In the active region of the output characteristics, the control of the gate current the drain current is due to the possibility to control the level of majority-carrier injection from the source transition. The closed-form expression for the current gain allows to identify the structure parameters that affect it. It shown that, under suitable conditions, a substantial current amplification can be observed. The model has been found to be in good agreement with the results obtained on experimental devices.

A quasi-one-dimensional analysis of vertical JFET devices operated in the bipolar mode

The fabrication and characterization of a family of power bipolar-mode junction FETs (BMFETs) are reported. Blocking voltages up to 1000 V or currents up to 18 A (corresponding to 800 A/cm/sup 2/) have been obtained. The experimental results are used to get an insight into the physics of BMFET operation and to extract the basic design criteria for these structures. The performance of the BMFET is compared with that of the bipolar transistor, showing it to be superior. >

Performance analysis of a bipolar mode FET (BMFET) with normally off characteristics

The first realization of a power vertical JFET operated in the bipolar mode (BJFET) with normally off behavior is reported. The structure combines minority carrier injection from the gate region in the on-state, and lateral pinch-off of the channel, due to the built-in voltage, in the off-state. The realized devices show high blocking voltages, up to 900 V, with zero gate bias, and have extremely low on-resistance. Fast switching speeds with forced gate turn-off times as low as 100 ns for devices of 600-V blocking voltages have been obtained.

High-voltage bipolar mode JFET with normally off characteristics

The negative resistance induced by space-charge effects in bulk semiconductor devices subjected to avalanche multiplication has been studied to clarify the physics of this phenomenon and the validity of the assumptions made by other authors. On the basis of the numerical results, an analytical model is proposed, using the regional approximation to evaluate the field along the device and the J-V characteristic. Both the numerical and the analytical results show the role played by the injection of electrons from the cathode and the velocity saturation for the onset of negative resistance, as well as the role of hole injection from the multiplication region near the anode into the bulk for the subsequent voltage lowering. Experimental results are in good agreement with the analytical model in a wide range of device parameters.

Negative resistance induced by avalanche injection in bulk semiconductors

On the basis of the physical picture obtained by a detailed two-dimensional numerical simulation, an analytical model is developed for the I-V characteristics of a normally-off bipolar-mode FET structure. The numerical results show that the device has basically two modes of operation. When the minority-carrier injection from the gate is negligible, the device operation is governed by the modulation of the potential barrier in the channel due to the gate and drain voltages. This gives rise to an exponential shape of the I-V characteristics in the subthreshold regime, while for larger drain currents a transition to a triodelike shape takes place. The second mode of operation is due to the injection of minority carriers from the gate. This bipolar mode of operation is modeled according to a regional approximation method. The limits of the proposed quasi one-dimensional analysis are discussed by comparisons with the two-dimensional numerical results. The comprehensive analytical model obtained gives results in very good agreement with the numerical simulations and can be used to assess the influence of the various geometrical and physical parameters on the performances of the device.

A. Caruso

Papers

A quasi-one-dimensional analysis of vertical JFET devices operated in the bipolar mode

Performance analysis of a bipolar mode FET (BMFET) with normally off characteristics

High-voltage bipolar mode JFET with normally off characteristics

Negative resistance induced by avalanche injection in bulk semiconductors

Two-dimensional analysis of the I-V characteristics of normally-off bipolar-mode FET devices