This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-?m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 × 265 ?m2.

/pdf/a-10-bit-50-ms-s-sar-adc-with-a-monotonic-capacitor-hcl5rch1mj.pdf

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

http://faculty.poly.edu/~tsr/wp-content/uploads/publications/abstract17.pdf

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

This paper presents two 1.8 GHz CMOS voltage-controlled oscillators (VCOs), tuned by an inversion-mode MOS varactor and an accumulation-mode MOS varactor, respectively. Both VCOs show a lower power consumption and a lower phase noise than a reference VCO tuned by a more commonly used diode varactor. The best overall performance is displayed by the accumulation-mode MOS varactor VCO. The VCOs were implemented in a standard 0.6 /spl mu/m CMOS process.

On the use of MOS varactors in RF VCOs

Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 /spl mu/m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%.

/pdf/reducing-mosfet-1-f-noise-and-power-consumption-by-switched-1dgtz1md7r.pdf

Reducing MOSFET 1/f noise and power consumption by switched biasing

"Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

/pdf/reducing-mosfet-1-f-noise-and-power-consumption-by-switched-4rlksm1x1t.pdf

Reducing MOSFET 1/f noise and power consumption by "Switched biasing"

A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate with good power efficiency. The single-sided overrange architecture achieves a 25% higher power efficiency of the SA-ADC compared with the conventional overrange architecture, and look-ahead logic is used to minimize logic delay in the SA-ADC. For the T&H, three techniques are presented enabling a high bandwidth and linearity and good timing alignment. Single channel performance of the ADC is 6.9 ENOB at an input frequency of 4 GHz. Multichannel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz. The FoM of the complete ADC including T&H is 0.6 pJ per conversion step. An improved version is presented as well and achieves an SNDR of 8.6 ENOB for low sample rates, and, with increased supply voltage, it reaches a sample rate of 1.8 GS/s with 7.9 ENOB at low input frequencies and an ERBW of 1 GHz. At fin = 3.6 GHz, the SNDR is still 6.5 ENOB, and total timing error including jitter is 0.4 ps rms.

/pdf/a-1-35-gs-s-10-b-175-mw-time-interleaved-ad-converter-in-0-4n8k9ot870.pdf

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS

A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a one-sigma offset of 8mV, the circuit consumes 92fJ/decision at 1.2V supply. It has an input equivalent noise of 1.5mV and requires only 18ps setup plus hold time.

/pdf/a-low-offset-double-tail-latch-type-voltage-sense-amplifier-2tczuofbn5.pdf

A Low-Offset Double-Tail Latch-Type Voltage Sense Amplifier

The implications of intrinsic 1/f device noise reduction in MOS transistors due to periodic on-off switching in a CMOS ring oscillator are explored. It is shown that maximising the amplitude of oscillation helps to reduce the close-in phase noise. Measurement results, corrected for amplitude-dependent upconversion and effective bias show an improvement of 8 dB in phase noise at 1KHz frequency offset from the carrier at 4.5 dB increase in carrier power.

/pdf/reduction-of-intrinsic-1-f-device-noise-in-a-cmos-ring-3xdtz1pwgm.pdf

Reduction of intrinsic 1/f device noise in a CMOS ring oscillator

A CMOS temperature switch with uncalibrated high temperature accuracy is presented. The circuit is based on the classical CMOS bandgap reference structure, using parasitic PNPs and a PTAT multiplier. The circuit was designed in a standard digital 0.18 µm CMOS process. The temperature switch has a in-designed hysteresis of 1.2° C around a threshold value of 128° C. At the switching-threshold all matched transistors have also matched operating conditions, yielding a temperature threshold that is highly independent of transistor output resistance and supply voltage. With a chip area of only 0.03 mm2:, the on-wafer 3σ spread of the threshold temperature is 1.1° C. Power consumption is only 15 µA at 1 Volt supply.

A 1-V 15&#181;W high-precision temperature switch

Spectrum measurement results of a CMOS ring oscillator are presented that show a 10 dB decrease in 1/f noise induced phase noise at a 2 dB increase in carrier power. Simple ring oscillator theory predicts that the 1/f noise induced phase noise is independent of carrier power. It is shown that an increase in the amplitude of oscillation is accompanied by a reduction of the intrinsic 1/f noise of the periodically switched MOS transistors in the ring. A net reduction of the 1/f noise of a periodically switched NMOS transistor of more than 12 dB is measured in the baseband.

/pdf/reduction-of-the-1-f-noise-induced-phase-noise-in-a-cmos-20tz67gd0e.pdf

A.J.M. van Tuijl

Papers

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS

A Low-Offset Double-Tail Latch-Type Voltage Sense Amplifier

Reduction of intrinsic 1/f device noise in a CMOS ring oscillator

A 1-V 15µW high-precision temperature switch

Reduction of the 1/f noise induced phase noise in a CMOS ring oscillator by increasing the amplitude of oscillation

A.J.M. van Tuijl

Papers

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS

A Low-Offset Double-Tail Latch-Type Voltage Sense Amplifier

Reduction of intrinsic 1/f device noise in a CMOS ring oscillator

A 1-V 15&#181;W high-precision temperature switch

Reduction of the 1/f noise induced phase noise in a CMOS ring oscillator by increasing the amplitude of oscillation

A 1-V 15µW high-precision temperature switch