This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

/pdf/low-power-low-phase-noise-differentially-tuned-quadrature-q31y9qihqr.pdf

Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

This paper presents two 1.8 GHz CMOS voltage-controlled oscillators (VCOs), tuned by an inversion-mode MOS varactor and an accumulation-mode MOS varactor, respectively. Both VCOs show a lower power consumption and a lower phase noise than a reference VCO tuned by a more commonly used diode varactor. The best overall performance is displayed by the accumulation-mode MOS varactor VCO. The VCOs were implemented in a standard 0.6 /spl mu/m CMOS process.

On the use of MOS varactors in RF VCOs

A harmonic oscillator topology displaying an improved phase noise performance is introduced in this paper. Exploiting the advantages yielded by operating the core transistors in class-C, a theoretical 3.9 dB phase noise improvement compared to the standard differential-pair LC-tank oscillator is achieved for the same current consumption. Further benefits derive from the natural rejection of the tail bias current noise, and from the absence of parasitic nodes sensitive to stray capacitances. Closed-form phase-noise equations obtained from a rigorous time-variant circuit analysis are presented, as well as a time-variant study of the stability of the oscillation amplitude, resulting in simple guidelines for a reliable design. Furthermore, the analysis of phase noise is extended to encompass a general harmonic oscillator, showing that all phase noise relations previously obtained for specific LC oscillator topologies are special cases of a very general and remarkably simple result.

Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise

A 1.8-GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1.8-GHz carrier while drawing 3.2 mA from a 1.5-V supply. The impacts of wideband operation on start-up constraints and phase noise are discussed. Tuning range is analyzed in terms of fundamental dimensionless design parameters yielding useful design equations. An amplitude calibration technique is used to stabilize performance across the wide band of operation. This amplitude control scheme not only consumes negligible power and area without degrading the phase noise, but also proves to be instrumental in sustaining the VCO performance in the upper end of the frequency range.

A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration

Electrical noise and RTS fluctuations in advanced CMOS devices

The tuning curve of an LC-tuned voltage-controlled oscillator (VCO) substantially deviates from the ideal curve 1//spl radic/(LC(V)) when a varactor with an abrupt C(V) characteristic is adopted and the full oscillator swing is applied directly across the varactor. The tuning curve becomes strongly dependent on the oscillator bias current. As a result, the practical tuning range is reduced and the upconverted flicker noise of the bias current dominates the 1/f/sup 3/ close-in phase noise, even if the waveform symmetry has been assured. A first-order estimation of the tuning curve for MOS-varactor-tuned VCOs is provided. Based on this result, a simplified phase-noise model for double cross-coupled VCOs is derived. This model can be easily adapted to cover other LC-tuned oscillator topologies. The theoretical analyses are experimentally validated with a 0.25 /spl mu/m CMOS fully integrated VCO for 5 GHz wireless LAN receivers. By eliminating the bias current generator in a second oscillator, the close-in phase noise improves by 10 dB and features -70 dBc/Hz at 10 kHz offset. The 1/f/sup 2/ noise is -132 dBc/Hz at 3 MHz offset. The tuning range spans from 4.6 to 5.7 GHz (21%) and the current consumption is 2.9 mA.

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply.

/pdf/a-low-phase-noise-5-ghz-cmos-quadrature-vco-using-582qevjd7j.pdf

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling

Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 /spl mu/m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%.

/pdf/reducing-mosfet-1-f-noise-and-power-consumption-by-switched-1dgtz1md7r.pdf

Reducing MOSFET 1/f noise and power consumption by switched biasing

"Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

/pdf/reducing-mosfet-1-f-noise-and-power-consumption-by-switched-4rlksm1x1t.pdf

Reducing MOSFET 1/f noise and power consumption by "Switched biasing"

This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence the oscillator's close-in phase noise. More specifically, it is shown that the 1/f/sup 3/ phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1/f/sup 3/ phase noise than expected. It will be shown that this can be attributed to the intrinsic 1/f noise reduction effect due to periodic on-off switching.

/pdf/intrinsic-1-f-device-noise-reduction-and-its-effect-on-phase-2lzsias5na.pdf

S.L.J. Gierkink

Papers

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling

Reducing MOSFET 1/f noise and power consumption by switched biasing

Reducing MOSFET 1/f noise and power consumption by "Switched biasing"

Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators