VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

Advanced packaging

The quality of delay testing focused on small delay defects is not clear when traditional fault models are used. We therefore evaluated the feasibility of using the statistical delay quality model (SDQM) - which reflects fabrication process quality, design delay quality, test timing accuracy, and test pattern quality - by using a commercial automatic test program generation (ATPG) tool to apply it to a large data set. The SDQM can also provide a measure predicting the defect level of a chip, and by simulating test patterns we show experimentally here that this measure can be calculated within a reasonable CPU time when using a reasonable amount of memory. Because we found when using SDF information to calculate path lengths accurately that the transition test patterns are not good at detecting small delay defects in long paths, a new test algorithm that detects small delay defects should be developed

Invisible delay quality - SDQM model lights up what could not be seen

This work proposes an effective method for applying fine-delay fault testing in order to improve defect coverage of especially resistive opens. The method is based on grouping conventional delay-fault patterns into sets of almost equal-length paths. This narrows the overall path length distribution and allows running the pattern sets at a higher speed, thus enabling the detection of small delay faults. These small delay faults are otherwise undetectable because they are masked by longer paths. A requirement for this method is to have hazard-free paths. To obtain these (almost) hazard-free paths we use a fast and simple postprocessing step that filters out paths with hazards. The experimental data shows the effectiveness and the necessity of this filtering process.

On hazard-free patterns for fine-delay fault testing

Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The power supply noise impact on delay must be taken into account when delay tests are applied.

/pdf/power-supply-noise-in-delay-testing-49prchpbib.pdf

Power Supply Noise in Delay Testing

Defects due to process-design interaction have a systematic nature. Therefore they can have a profound impact on yield. The capability to detect (and correct) them is a requirement to continue to follow Moore's law. Most of the systematic defects are detected during the process development. These defects are detectable with test structures or visual inspection tools. However some process marginalities are only show-up in the topology of 'real' designs. Moreover, these defects are often not detectable with stuck-at testing. We show two examples of process related defects which could only be detected with more advanced test methods such as transition fault testing and low voltage testing. To correct systematic problems, however, one should not only have the capability to detect defects but also to identify them. Our examples show that other tests could have been far more sensitive in detecting systematic issues. Therefore the detection of systematic defects gives new requirements to test suites and can only be achieved with a shift in the position of manufacturing test.

Systematic defects in deep sub-micron technologies

Intra-gate resistive open defects not only cause sequential behaviour in CMOS memory address decoders, but also lead to delay behaviour. This paper evaluates the fault coverage of the resistive open defects in the memory address decoders. It shows that both the strong and the weak open defects are not completely covered by applying the well-known March tests and special test pattern sequences published in the literature. We demonstrate that the fault coverage is increased by varying the duty cycle of the internal clock of the address decoder. For the self-timed memories, we introduce a simple DFT technique to control the duty cycle of the internal clock which activates/deactivates the word lines. Using defect-oriented test, we also created a fault dictionary based on the defect location, transistor types, the terminal name and also the faulty behaviour. The fault dictionary in combination with the bit-map fail data will facilitate the localization of the open defects.

New test methodology for resistive open defect detection in memory address decoders

This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products; i.e., low defect-per-million (DPM) level, which is driving the semiconductor market today. The above test conditions have been validated to screen out bad devices on real silicon (a test-chip) built on CMOS 0.18 /spl mu/m technology. The IFA (inductive fault analysis) based simulation technique leads to an efficient fault coverage and DPM estimator, which helps the customers upfront to make decisions on test algorithm implementations under different stress conditions in order to reduce the number of test escapes.

https://hal.archives-ouvertes.fr/hal-00181553/document

A. Majhi

Papers

On hazard-free patterns for fine-delay fault testing

Power Supply Noise in Delay Testing

Systematic defects in deep sub-micron technologies

New test methodology for resistive open defect detection in memory address decoders

Memory Testing Under Different Stress Conditions: An Industrial Evaluation