The paper reviews our recent progress and current challenges in implementing advanced gate stacks composed of high-κ dielectric materials and metal gates in mainstream Si CMOS technology. In particular, we address stacks of doped polySi gate electrodes on ultrathin layers of high-κ dielectrics, dual-workfunction metal-gate technology, and fully silicided gates. Materials and device characterization, processing, and integration issues are discussed.

Advanced high-κ dielectric stacks with polySi and metal gates: recent progress and current challenges

We demonstrate a new MOSFET on ultra-thin BOX that allows wide-range back-bias control in low-power and high-performance applications. The back gate is effective not only to increase the drive current by about 20% in active mode but also in reduce the off-current by an order of magnitude in stand-by mode. We have also demonstrated tunable-threshold-voltage technology for devices with metal gates and ion implantation for V/sub th/ control. The target V/sub th/ for low-power applications was achieved by using ion implantation for V/sub th/ control. We propose a 6-transistor SRAM memory cell in which we obtain even more benefit from the new device structure by adding a feedback mechanism. A proposed 6-Tr SRAM memory cell is shown to dramatically improve SNM characteristics at the 65-nm technology nodes, and this effect will also apply at finer nodes.

Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control

High-k dielectrics have been intensively investigated during the last decade, and their performance as a gate dielectric has been improved to the level of conventional SiO2-based gate dielectric at an equivalent oxide thickness (EOT) ~1 nm. The understanding on metal electrodes and their interaction with the underlying high-k dielectric has been expanded, and various CMOS device results with metal electrode/high-k gate dielectric stacks have been reported, indicating the maturity of this technology. The next challenges lie in scaling the gate stack to 0.5-nm EOT to extend the usage of the metal electrode/high-k gate dielectric stacks to future technology generations. A new class of high-k dielectric that has a dielectric constant higher than 26 and a barrier height of ~5.0 eV and above will be needed to achieve this target. Recent progress in this so-called higher k dielectric research is summarized, and its benefit to the gate leakage current is discussed. This paper also reviews various extrinsic and intrinsic process-related defects in the deep subnanometer gate stacks and the potential challenges in implementing such a gate-stack system.

Metal Electrode/High- $k$ Dielectric Gate-Stack Technology for Power Management

Metal-gate FinFETs were fabricated using complete gate silicidation with Ni, combining the advantages of metal-gate and double-gate transistors. NiSi-gate workfunction control is demonstrated using silicide induced impurity segregation of As, P, and B over a range of 400 mV. High device performance is achieved by integrating the NiSi metal gate with an epitaxial raised source/drain, silicided separately with CoSi/sub 2/. Process considerations for this dual silicide integration scheme are discussed. Poly-Si gated FinFETs are also fabricated and used as references for workfunction and transconductance.

Fabrication of metal gated FinFETs through complete gate silicidation with Ni

Complete gate silicidation has recently been demonstrated as an excellent technique for the integration of metal gates into MOSFETs. From the various silicide gate materials NiSi has been shown to be the most scalable. In this paper, a versatile method for controlling the workfunction of an NiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect of various impurities including B, P, As, Sb, In, and Al is described. The segregation of the impurities from the poly-Si to the silicide interface during the silicidation step is found to cause the NiSi workfunction shift. The effect of the segregated impurities on gate capacitance, mobility, local workfunction stability, and adhesion is studied.

Threshold voltage control in NiSi-gated MOSFETs through SIIS

Fully depleted SOI (FDSOI) devices with undoped channel require metal gates to achieve correct threshold voltages We demonstrate metal gate FDSOI devices using NiSi gates with symmetric V/sub t/ for both NMOS and PMOS devices Metal gates are stable on 2 nm gate oxide and show capacitance equivalent gate oxide thickness (CET) 06 nm thinner than poly gates The gate leakage current is up to two orders of magnitude lower and high mobility is achieved (peak electron mobility 670 cm/sup 2//Vs and 170 cm/sup 2//Vs for holes)

Nickel silicide metal gate FDSOI devices with improved gate oxide leakage

We demonstrate 25 nm mid-gap metal gate fully-depleted silicon on insulator (FDSOI) devices with the highest reported drive current for a single-gate PMOS device (I/sub on/=789 /spl mu/A//spl mu/m and I/sub off/=27 nA//spl mu/m for V/sub gs/-V/sub t/=1.25 V). We observe electron and hole mobility degradation for very thin channels (/spl sim/7 nm). Devices show good hot carrier and gate dielectric reliability.

A. Marathe

Papers

Nickel silicide metal gate FDSOI devices with improved gate oxide leakage

High performance 25 nm FDSOI devices with extremely thin silicon channel