A
A. Singh
Researcher at Intel
Publications - 11
Citations - 2146
A. Singh is an academic researcher from Intel. The author has contributed to research in topics: Clock gating & Router. The author has an hindex of 7, co-authored 11 publications receiving 2095 citations.
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Proceedings ArticleDOI
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
Sriram R. Vangal,Jason Howard,G. Ruhl,Saurabh Dighe,H. Wilson,J. Tschanz,D. Finan,P. Iyer,A. Singh,Tiju Jacob,Shailendra Jain,S. Venkataraman,Y. Hoskote,Nitin Borkar +13 more
TL;DR: A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz, designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
Journal ArticleDOI
A 5-GHz Mesh Interconnect for a Teraflops Processor
TL;DR: A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W.
Journal ArticleDOI
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
Sriram R. Vangal,Jason Howard,Greg Ruhl,Saurabh Dighe,H. Wilson,James W. Tschanz,D. Finan,A. Singh,Tiju Jacob,Shailendra Jain,Vasantha Erraguntla,Clark Roberts,Yatin Hoskote,Nitin Borkar,Shekhar Borkar +14 more
TL;DR: In this paper, an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz.
Proceedings ArticleDOI
A 5.1GHz 0.34mm 2 Router for Network-on-Chip Applications
TL;DR: A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture that combines 102 GB/s of raw bandwidth with low fall-through latency.
Journal ArticleDOI
Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core
Daniel J. Deleganes,Micah Barany,George L. Geannopoulos,Kurt Kreitzer,M. Morrise,D. Milliron,A. Singh,Sapumal Wijeratne +7 more
TL;DR: Low-voltage-swing logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design of Pentium/spl reg/ 4 processor architecture.