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Shailendra Jain
Researcher at Intel
Publications - 15
Citations - 2766
Shailendra Jain is an academic researcher from Intel. The author has contributed to research in topics: CMOS & Network on a chip. The author has an hindex of 10, co-authored 15 publications receiving 2711 citations.
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Proceedings ArticleDOI
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
Sriram R. Vangal,Jason Howard,G. Ruhl,Saurabh Dighe,H. Wilson,J. Tschanz,D. Finan,P. Iyer,A. Singh,Tiju Jacob,Shailendra Jain,S. Venkataraman,Y. Hoskote,Nitin Borkar +13 more
TL;DR: A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz, designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
Proceedings ArticleDOI
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
Jason Howard,Saurabh Dighe,Yatin Hoskote,Sriram R. Vangal,D. Finan,G. Ruhl,David Jenkins,H. Wilson,Nitin Borkar,Gerhard Schrom,Fabrice Pailet,Shailendra Jain,Tiju Jacob,Satish Yada,Sravan K. Marella,Praveen Salihundam,Vasantha Erraguntla,Michael Konow,Michael Riepen,Guido Droege,Joerg Lindemann,Matthias Gries,Thomas Apel,Kersten Henriss,Tor Lund-Larsen,Sebastian Steibl,Shekhar Borkar,Vivek De,Rob F. Van der Wijngaart,Timothy G. Mattson +29 more
TL;DR: This paper presents a prototype chip that integrates 48 Pentium™ class IA-32 cores on a 6×4 2D-mesh network of tiled core clusters with high-speed I/Os on the periphery to realize a data-center-on-a-die microprocessor architecture.
Journal ArticleDOI
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
Sriram R. Vangal,Jason Howard,Greg Ruhl,Saurabh Dighe,H. Wilson,James W. Tschanz,D. Finan,A. Singh,Tiju Jacob,Shailendra Jain,Vasantha Erraguntla,Clark Roberts,Yatin Hoskote,Nitin Borkar,Shekhar Borkar +14 more
TL;DR: In this paper, an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz.
Journal ArticleDOI
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
Jason Howard,Saurabh Dighe,Sriram R. Vangal,G. Ruhl,Nitin Borkar,Shailendra Jain,Vasantha Erraguntla,Michael Konow,Michael Riepen,Matthias Gries,Guido Droege,Tor Lund-Larsen,Sebastian Steibl,S. Borkar,Vivek De,R Van Der Wijngaart +15 more
TL;DR: A multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture that uses message passing while exploiting 384 KB of on-die shared memory for fine grain power management.
Proceedings ArticleDOI
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS
Shailendra Jain,Surhud Khare,Satish Yada,V Ambili,Praveen Salihundam,Shiva Ramani,Sriram Muthukumar,Manali Ramakrishnan Srinivasan,Arun Kumar,Shasi Kumar Gb,Rajaraman Ramanarayanan,Vasantha Erraguntla,Jason Howard,Sriram R. Vangal,Saurabh Dighe,Greg Ruhl,Paolo Aseron,H. Wilson,Nitin Borkar,Vivek De,Shekhar Borkar +20 more
TL;DR: An IA-32 processor fabricated in 32nm CMOS technology is described, demonstrating a reliable ultra-low voltage operation and energy efficient performance across the wide voltage range from 280mV to 1.2V.