Showing papers by "Adam William Saxler published in 2006"

40-W/mm Double Field-plated GaN HEMTs

Abstract: Field plate technologies have dramatically raised the benchmarks of GaN-based high-electron-mobility transistors (HEMTs). Greater than 30 W/mm power density was demonstrated with gate-connected field plates'. The drawback of additional feedback capacitances added by the field plates was then addressed using source-termination, achieving 21dB large-signal gain and 20-W/mm power density at 4 GHz"l. Recently, multiple field plates were pursued for further improvements""v I. Here we present double field-plated GaN HEMTs with increased power density and robustness. The devices in this study consisted of a Cree HPSI SiC substrate, a 2-4 ptm thick insulating GaN buffer, a thin AlN interlayer and an Al0.26Gao.74N barrier layer. The GaN buffer was doped with Fe for enhanced resistivity and the AlN interlay was included to achieve a high charge-mobility product without the complication of increasing the Al mole fraction of the top AlGaN layer. The device has a first field plate (FP1) integrated with the gate for both reduced gate resistance and elimination of electron trapping. The task of further tailoring the electric field and attaining a higher breakdown voltage is accomplished by a second field plate (FP2), placed on the drain side of the first field plate. FP2 is electrically connected to the source of the HEMT to minimize feedback capacitance. When designed properly, the double field-plated devices can offer a more optimal electric field distribution, improving performance and robustness. Targeting high-power operation at C band, the length of FP1 was set at LF1=0.3-0.5 ptm and FP2 at LF2=0.9-1.2 ptm. The SiN dielectric thickness under FP1 and FP2 was 100 nm and 200 nm, respectively. The device fabrication steps were similar to previous reports,"" except for the gate formation, where the integrated gate and FP1 were deposited on the SiN layer with a previously etched gate opening. Devices of four configurations were fabricated for a direct comparison. Device A had no field plate. Device B had double field plates, both connected to the gate. Device C had double field plates, FP, connected to the gate and FP2 connected to the source. Device D had a single field plate connected to the source. The gate length was about 0.55 ptm and gate-drain separation was 3.5 ptm. Typical devices showed -4 V pinch-off voltage and >1.2 A/mm full channel current. While circuit element extraction from S-parameters revealed practically the same current gain cut-off frequency of 30-35 GHz for the intrinsic devices, the maximum stable gains (MSG) varied based on the extrinsic parasitics. In particular, with LF1=0.3 pim and LF2=0.9 pim, MSG values at 10-GHz and 41 V for devices A, B, C and D were 15.6 dB, 11.2 dB, 16.7 dB and 17.1dB, respectively. It is expected that device B with both field plates connected to the gate has a high feedback capacitance, hence a much lower MSG than the non-field-pate device A. With FP2 connected to the source, however, device C actually exhibited higher MSG than the non-field-pate device. This is attributed to the Faraday shielding effect by the source field plate, which reduces the feedback capacitance. Although device D, with a single field plate connected to the source, showed 0.4-dB higher gain than device C, the less-optimum electric field distribution made it less robust and more prone to degradation at high operation voltages. Power measurements were performed with a load-pull system at 4 GHz. As intended, device C showed the best combination of output power, gain, power-added efficiency and robustness. A 246-pim-wide device with LF1=0.5 pim and LF2=1 .2 pim was able to be biased at 135 V and achieved a continuous-wave (CW) power density of 41.4 W/mm, along with 16-dB associated gain and 60% PAE. This is a significant improvement over previous result of 32.2 W/mm, 14 dB associated gain and 54.8% PAE by single-field-plated GaN HEMTs. Initial reliability tests showed that the double-fieldplated device had no degradation after 100-hour RF operation at 80 V while generating CW output power of 25 W/mm. In summary, a double-field-plate structure has been developed to extend the performance limit of microwave GaN HEMTs. The first field plate offers a high gate conductance and prevents the onset of trapping; while the 2nd field plate maximizes operation voltage without additional feedback capacitances. 41.4 W/mm CW power density was obtained, establishing a new state-of-the-art for microwave devices.

Semiconductor devices including implanted regions and protective layers and methods of forming the same

Abstract: Methods of forming a semiconductor device include forming a protective layer (24) on a semiconductor layer, implanting ions having a first conductivity type through the protective layer (24) into the semiconductor layer to form an implanted region (31) of the semiconductor layer, and annealing the semiconductor layer and the protective layer (24) to activate the implanted ions. An opening is formed in the protective layer (24) to expose the implanted region (31) of the semiconductor layer, and an electrode is formed in the opening. A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer (24) on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact (30) extending through the protective layer to the semiconductor layer.

Binary group iii-nitride based high electron mobility transistors and methods of fabricating same

Abstract: Aluminum free high electron mobility transistors (HEMTs) and methods of fabricating aluminum free HEMTs are provided In some embodiments, the aluminum free HEMTs include an aluminum free Group III-nitride barrier layer, an aluminum free Group III-nitride channel layer on the barrier layer and an aluminum free Group III-nitride cap layer on the channel layer

Heterojunction transistors including energy barriers and related methods

Abstract: A heterojunction transistor may include a channel layer (14) comprising a Group III nitride, a barrier layer (16) comprising a Group III nitride on the channel layer, and an energy barrier (30, 32, 34) comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.

Thick semi-insulating or insulating epitaxial gallium nitride layers and devices incorporating same

Abstract: Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 µm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 µm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.

Rare earth doped layer or substrate for light conversion

Abstract: A solid state light emitting device comprising an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of the active region. The active region emits light at a predetermined wavelength in response to an electrical bias across the doped layers. An absorption layer of semiconductor material is included that is integral to said emitter structure and doped with at least one rare earth or transition element. The absorption layer absorbs at least some of the light emitted from the active region and re-emits at least one different wavelength of light. A substrate is included with the emitter structure and absorption layer disposed on the substrate.

Heterojunction transistors including energy barriers

Abstract: A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer Related methods are also discussed

Quantum wells for light conversion

Abstract: A solid state light emitting device according to the present invention comprises an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of said active region. The active region emits light at a first wavelength in response to an electrical bias across said doped layers. A quantum well structure is included that is integral to the emitter structure and has a plurality of layers having a composition and thickness such that the quantum well structure absorbs at least some of the light emitted from the active region and re-emits light of at least one different wavelength of light from said first wavelength.

High-Efficiency Amplifiers Using AlGaN/GaN HEMTs on SiC

Abstract: GaN HEMTs on SiC are applied to high-efficiency power amplifier designs. Several class-E hybrid power amplifiers based on the GaN HEMT cell were designed and tested. Around 2 GHz, the first amplifier provides 10 watts CW with associated PAE of 85% and gain of 12 dB. Other higher frequency designs with the same transistor cell provide 10 watts and 80% PAE centered around 2.8 GHz and also 10 watts and 76% PAE centered around 3.4 GHz. Also, a larger-periphery class-E amplifier operating at 2 GHz with a peak power of 63 watts and 75% PAE has been demonstrated using GaN HEMT technology.

Semiconductor device including implanted region and protective layer, and method of forming the same

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device, including an implanted region and a protective layer, and to provide a method of forming the semiconductor device. SOLUTION: The method of forming the semiconductor device comprises the steps of forming the protective layer on a semiconductor layer; implanting an ion having a first conductivity type into the semiconductor layer through the protective layer for forming the implanted region of the semiconductor layer; and annealing the semiconductor layer and the protective layer for making the implanted ions activate. An opening is formed in the protective layer for exposing the implanted region of the semiconductor layer, and an electrode is formed in the opening. A semiconductor structure includes a group III nitride semiconductor layer, the protective layer on the semiconductor layer, a distribution of injected dopant within the semiconductor layer, and an ohmic contact existing extended to the semiconductor layer through the protective layer. COPYRIGHT: (C)2007,JPO&INPIT

Heterojunction transistor having energy barrier, and related method

Abstract: PROBLEM TO BE SOLVED: To improve confinement of carriers in a channel. SOLUTION: The heterojunction transistor can be provided with a channel layer which includes a group III nitride, a barrier layer which is on the channel layer and includes a group III nitride and an energy barrier which is on the channel layer and includes a layer of a group III nitride having indium in such a way that the channel layer is between the barrier layer and the energy barrier. The barrier layer can exhibit a larger bandgap than that of the channel layer. There is a possibility that the concentration of indium (In) in the energy barrier is higher than the concentration of indium (In) in the channel layer. The related method is presently being studied. COPYRIGHT: (C)2007,JPO&INPIT

Silicon carbide layer on diamond substrate for supporting group III nitride heterostructure device

Abstract: A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics.

Group iii nitride layers on silicon carbide substrates

Abstract: Group III nitride semiconductor device structures are provided that include a silicon carbide (SiC) substrate and a Group III nitride epitaxial layer above the SiC substrate. The Group III nitride epitaxial layer has a dislocation density of less than about 4x108 cm-2 and/or an isolation voltage of at least about 50V.

Method of fabricating seminconductor devices including self aligned refractory contacts

Abstract: Methods of forming semiconductor devices are provided by forming a semiconductor layer on a semiconductor substrate. A mask is formed on the semiconductor layer. Ions having a first conductivity type are implanted into the semiconductor layer according to the mask to form implanted regions on the semiconductor layer. Metal layers are formed on the implanted regions according to the mask. The implanted regions and the metal layers are annealed in a single step to respectively activate the implanted ions in the implanted regions and provide ohmic contacts on the implanted regions. Related devices are also provided.

Methods of fabricating strain balanced nitride heterojunction transistors

Abstract: A nitride based heterojunction transistor includes a substrate and a first Group III nitride layer, such as an AlGaN based layer, on the substrate. The first Group III-nitride based layer has an associated first strain. A second Group III-nitride based layer, such as a GaN based layer, is on the first Group III-nitride based layer. The second Group III-nitride based layer has a bandgap that is less than a bandgap of the first Group III-nitride based layer and has an associated second strain. The second strain has a magnitude that is greater than a magnitude of the first strain. A third Group III-nitride based layer, such as an AlGaN or AlN layer, is on the GaN layer. The third Group III-nitride based layer has a bandgap that is greater than the bandgap of the second Group III-nitride based layer and has an associated third strain. The third strain is of opposite strain type to the second strain. A source contact, a drain contact and a gate contact may be provided on the third Group III-nitride based layer. Nitride based heterojunction transistors having an AlGaN based bottom confinement layer, a GaN based channel layer on the bottom confinement layer and an AlGaN based barrier layer on the channel layer, the barrier layer having a higher concentration of aluminum than the bottom confinement layer, are also provided. Methods of fabricating such transistor are also provided.

Method for forming a composite substrate for a high power device in wide bandgap materials

Abstract: A method of forming a high-power, high-frequency device in wide bandgap semiconductor materials with reduced junction temperature, higher power density during operation and improved reliability at a rated power density is disclosed, along with resulting semiconductor structures and devices. The method includes adding a layer of diamond (11) to a silicon carbide wafer (10) to increase the thermal conductivity of the resulting composite wafer, thereafter reducing the thickness of the silicon carbide portion of the composite wafer while retaining sufficient thickness of silicon carbide to support epitaxial growth thereon, preparing the silicon carbide surface of the composite wafer for epitaxial growth thereon, and adding a Group III nitride HEMT to the prepared silicon carbide face of the wafer.

Group iii nitride field effect transistors

Abstract: Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (VDS) of about 56 volts, a gate to source voltage (Vgs) of from about -8 to about -14 volts and a temperature of about 140 °C for at least about 10 hours.

Structure and method for reducing forward voltage across a silicon carbide-group III nitride interface

Abstract: A structure is disclosed that reduces the forward voltage across the interface between silicon carbide and Group III nitride layers. The structure includes a conductive silicon carbide substrate and a conductive layer of aluminum gallium nitride on the silicon carbide substrate. The aluminum gallium nitride layer has a mole fraction of aluminum that is sufficient to bring the conduction bands of the silicon carbide substrate and the aluminum gallium nitride into close proximity, but less than a mole fraction of aluminum that would render the aluminum gallium nitride layer resistive.

Group iii nitride epitaxial layers on silicon carbide substrates

Abstract: A semiconductor structure is disclosed that includes a silicon carbide wafer having a diameter of at least 100 mm with a Group III nitride heterostructure on the wafer that exhibits high uniformity in a number of characteristics. These include: a standard deviation in sheet resistivity across the wafer less than three percent; a standard deviation in electron mobility across the wafer of less than 1 percent; a standard deviation in carrier density across the wafer of no more than about 3.3 percent; and a standard deviation in conductivity across the wafer of about 2.5 percent.

Method of forming heterojunction tranistors including energy barriers

Abstract: A heterojunction transistor may include a channel layer (14) comprising a Group III nitride, a barrier layer (16) comprising a Group III nitride on the channel layer, and an energy barrier (30, 32, 34) comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.