sultinanimplementation thatcannotbeexecuted within Multimedia applications usually havethroughput constraints. these timing constraints. Itisnecessary totakethetiming An implementation mustmeetthese constraints, while it constraints intoaccount while minimizing thebuffers. Sevminimizes resource usageandenergyconsumption. The eralapproaches havebeenproposed forminimizing buffer computeintensive kernels oftheseapplications areoften requirements underathroughput constraint. In[9], atechspecified asSynchronous Dataflow Graphs.Communica- nique basedonlinear programming isproposed tocalculate tionbetween nodesinthesegraphs requires storage space aschedule thatrealizes themaximalthroughput whileit whichinfluences throughput. We present exacttechniquestries tominimize buffer sizes. Hwangetal.propose aheuristochart thePareto spaceofthroughput andstorage trade- ticthatcantakeresource constraints into account [10]. This offs, whichcanbeusedtodetermine theminimal storage methodistargeted towards a-cyclic graphs anditalways spaceneeded toexecute agraphunderagiven throughputmaximizes throughput rather thanusing athroughput conconstraint. Thefeasibility oftheapproach isdemonstratedstraint. Thus,itcouldleadtoadditional resource requirewithanumberofexamples. ments. In[13], buffer minimization formaximal throughput ofa subclass ofSDFGs(homogeneous SDFGs) isachieved Categories andSubject Descriptors: C.3[Special-pur- viaaninteger linear programming approach. Ingeneral, poseandApplication-based Systems] Signal processing sys- theminimal buffer sizes obtained withthisapproach cantems notbetranslated toexact minimal buffer sizes forarbitrary GeneralTerms:Algorithms, Experimentation, Theory. SDFGs.We propose, incontrast toexisting work, an ex

Exploring Trade-Offs inBuffer Requirements and Throughput Constraints forSynchronous Dataflow Graphs*

Cooperation of CPU and hardware accelerator to accomplish computational intensive tasks, provides significant advantages in run-time speed and energy. Efficient management of data sharing among multiple computational kernels can rapidly turn into a complicated problem. The Accelerator coherency port (ACP) emerges as a possible solution by enabling hardware accelerators to issue coherent accesses to the memory space. In this paper, we quantify the advantages of using ACP over the traditional method of sharing data on the DRAM. We select the Xilinx ZYNQ as target and develop an infrastructure to stress the ACP and high-performance (HP) AXI interfaces of the ZYNQ device. Hardware accelerators on both of HP and ACP AXI interfaces reach full duplex data processing bandwidth of over 1.6 GBytes/s running at 125 MHz on a XC7Z020-1C device. The effect of background DRAM and cache traffic on the performance of accelerators is analyzed. For a sample image filtering task, the cooperative operation of CPU and ACP accelerator (CPU-ACP) gains a speed-up of 1.2X over CPU and HP acceleration (CPU-HP). In terms of energy efficiency, an improvement of 2.5 nJ (> 20%) is shown for each byte of processed data. This is the first work which represents detailed practical comparisons on the speed and energy efficiency of various processor-accelerator memory sharing techniques in a configurable heterogeneous platform.

/pdf/energy-and-performance-exploration-of-accelerator-coherency-4ctphga7p9.pdf

Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ

This book provides embedded software developers with techniques for programming heterogeneous Multi-Processor Systems-on-Chip (MPSoCs), capable of executing multiple applications simultaneously. It describes a set of algorithms and methodologies to narrow the software productivity gap, as well as an in-depth description of the underlying problems and challenges of todays programming practices. The authors present four different tool flows: A parallelism extraction flow for applications written using the C programming language, a mapping and scheduling flow for parallel applications, a special mapping flow for baseband applications in the context of Software Defined Radio (SDR) and a final flow for analyzing multiple applications at design time. The tool flows are evaluated on Virtual Platforms (VPs), which mimic different characteristics of state-of-the-art heterogeneous MPSoCs.

Programming Heterogeneous MPSoCs: Tool Flows to Close the Software Productivity Gap

Scalability is an important issue in large MPSoCs. MPSoCs may execute several applications in parallel, with dynamic workload, and tight QoS constraints. Thus, the MPSoC management must be distributed to cope with such constraints. This paper presents a distributed resource management in NoC-Based MPSoC, using a clustering method, enabling the modification of the cluster size at runtime. This work addresses the following distributed techniques: task mapping, monitoring and task migration. Results show an important reduction in the total execution time of applications, reduced number of hops between tasks (smaller communication energy), and a reclustering method through monitoring and task migration.

/pdf/distributed-resource-management-in-noc-based-mpsocs-with-42ct1ws8dz.pdf

Distributed resource management in NoC-based MPSoCs with dynamic cluster sizes

A first filter decision value is calculated for a block (10) of pixels (11, 13, 15, 17) in a video frame based on pixel values of pixels (11, 13, 15) in a first line (12) of pixels (11, 13, 15, 17) in the block (10) A second filter decision value is also calculated for the block (10) based on pixel values of pixels (21, 23, 25, 27) in a corresponding first line (22) of pixels (21, 23, 25, 27) in a neighboring block (20) in the video frame The first filter decision value is used to determine how many pixels in a line (12) of pixels (11, 13, 15, 17) in the block (10) to filter relative to a block boundary (1) between the block (10) and the neighboring block (20) The second filter decision value is used to determine how many pixels in a corresponding line (22) of pixels (21, 23, 25, 27) in the neighboring block to filter relative to the block boundary (1)

De-blocking filtering control

Future embedded systems demand multi-processor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semi-automated, time consuming and error prone. In this paper, we present a fully automated design flow to generate communication assist (CA) based multi-processor systems (CA-MPSoC). A worst-case performance model of our CA is proposed so that the performance of the CA-based platform can be analyzed before its implementation. The design flow provides performance estimates and timing guarantees for both hard real-time and soft real-time applications, provided the task to processor mappings are given by the user. The flow automatically generates a super-set hardware that can be used in all use-cases of the applications. The software for each of these use-cases is also generated including the configuration of communication architecture and interfacing with application tasks. CA-MPSoC has been implemented on Xilinx FPGAs for evaluation. Further, it is made available on-line for the benefit of the research community and in this paper, it is used for performance analysis of two real life applications, Sobel and JPEG encoder executing concurrently. The CA-based platform generated by our design flow records a maximum error of 3.4% between analyzed and measured periods. Our tool can also merge use-cases to generate a super-set hardware which accelerates the evaluation of these use-cases. In a case study with six applications, the use-case merging results in a speed up of 18 when compared to the case where each use-case is evaluated individually.

/pdf/ca-mpsoc-an-automated-design-flow-for-predictable-multi-4w7c2s77sm.pdf

CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications

The last decade a trend can be observed towards multi-processor Systems-on-Chip (MPSoC) platforms for satisfying the high computational requirements of modern multimedia applications. The research community has mainly focused on communication issues (e.g. bus vs. networks-on-chip). Real-time operating systems for MPSoCs however, have gotten very little attention. Existing techniques like rate-monotonic scheduling from the real-time community are rarely applicable, because contemporary high-performance media processors (like Cell, graphics processors) do not support preemption. Furthermore, rate-monotonic scheduling cannot deal with multiple (heterogeneous) processors, data dependencies, and dynamically varying execution times that characterize modern media applications. This paper proposes new techniques to manage the computational resources of MPSoCs at run-time. We compare a centralized resource manager (RM) to two versions (Credit based and Rate based) of a novel, more distributed RM. The distributed RMs are developed to cope with a larger number of processors as well as concurrently executing applications. Experiments show that our distributed resource managers are more scalable, deal better with application and user dynamics, and require less buffering, while effectively enforcing throughput constraints.

http://www.ece.nus.edu.sg/stfpage/eleak/pdf/samos11.pdf

Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms

In this paper, we present a high-throughput, area-efficient, hardware accelerator for the deblocking filter in H.264/AVC video compression standard. In order to achieve this goal, we start with algorithmic optimization and propose a novel decomposition of the filter kernels for the deblocking filter. The proposed decomposition reduces the number of adders by 51% and thereby greatly reduces the area requirement for its implementation. Subsequently, at architecture level, while using two identical filtering units, the transpose units are realized by efficient reuse of hardware resources to further reduce the area requirement. The two filtering units process the horizontal and vertical edges of the macro-block simultaneously and therefore further enhance the throughput of the hardware accelerator. Several other optimization techniques, such as reuse of intermediate results, pipelining, and merging of processing blocks on critical path, result in a hardware accelerator for deblocking filter with high throughput at one hand and less area in terms of equivalent gates count on the other, when compared with existing state-of-the-art hardware accelerators in the literature. While working at clock frequency of 166 MHz, synthesized under 0.18 µm CMOS standard cell technology, it easily meets the throughput requirements of all the levels in H.264/AVC video coding standard and consumes only 12.06 K gates (excluding SRAM).

/pdf/a-high-throughput-area-efficient-hardware-accelerator-for-2a2suz06yq.pdf

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

In this paper, we present a low-power, high-throughput hardware implementation of deblocking filter core in H.264/AVC for battery-powered multimedia electronic devices. The hardware implementation is based an optimized deblocking filter algorithm with 50% less number of addition operations. The evaluation of full or partial filtering skip scenarios is employed at an early stage in the filter processing chain to avoid un-necessary operations. Moreover, independent processing blocks are identified and are implemented with gated clock. Thus an efficient control block to activate/deactivate these independent processing blocks dynamically and pipeline implementation enable us to achieve low-power at one hand and high-throughput design for deblocking filter on the other. Experimental results suggest that the dynamic power consumption is reduced up to 50%, when compared with state-of-the-art designs in the literature. The deblocking filter core consumes 43 mW dynamic power on a Xilinx Virtex II FPGA and consumes 16.36 µW, when synthesized using 0.18µm CMOS standard cell library. The FPGA implementation on Virtex II can work at 76 MHz whereas the maximum operating frequency for 0.18µm process technology is 200 MHz. Our deblocking filter hardware implementation can easily provide real-time filtering operation for full-HD video format (1920×1080) @ 30 fps with an operating frequency as low as 59 MHz.

/pdf/low-power-high-throughput-deblocking-filter-for-h-264-avc-31uidm6nco.pdf

Low-power, high-throughput deblocking filter for H.264/AVC

Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadlines. These multiprocessors are increasingly becoming heterogeneous for reasons of cost and power. Design space exploration (DSE) of application mapping becomes a major design decision in such systems. The time spent in DSE becomes even greater with multiple applications executing concurrently. Methods have been proposed to automate generation of multiprocessor designs and prototype them on FPGAs. However, only few are able to support heterogeneous platforms. This is because heterogeneous processors require different types of inter-processor communication interfaces. So when we choose a different processor for a particular task, the communication infrastructure of the processor also has to change. In this paper, we present a module that integrates in a multiprocessor design generation flow and allows heterogeneous platform generation. This module is area efficient and fast. The DSE shows that up to 31% FPGA area can be saved when heterogeneous design is used as compared to a homogeneous platform. Moreover, the performance of the application also improves significantly.

/pdf/enabling-mpsoc-design-space-exploration-on-fpgas-44y0zj229c.pdf

Ahsan Shabbir

Papers

CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications

Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

Low-power, high-throughput deblocking filter for H.264/AVC

Enabling MPSoC design space exploration on FPGAs