Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

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3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

This paper is a review of the catalytic chemical vapor deposition (Cat-CVD) method and properties of silicon-based thin films, such as amorphous-silicon (a-Si), polycrystalline-silicon (p-Si) and silicon nitride (SiNx) films, prepared by the Cat-CVD method. In the Cat-CVD method, also known as the hot-wire CVD (HWCVD) method, deposition gases are decomposed by catalytic cracking reactions with a heated catalyzer placed near the substrates, so that films are deposited at low substrate temperatures around 300°C without any help from the plasma. After explaining the deposition system and deposition mechanism, the properties of Cat-CVD a-Si, p-Si and SiNx films are described and the results are compared with those obtained by the conventional plasma CVD (PCVD) method. The superiority of the Cat-CVD method over the PCVD method is demonstrated.

https://iopscience.iop.org/article/10.1143/JJAP.37.3175/pdf

Formation of Silicon-Based Thin Films Prepared by Catalytic Chemical Vapor Deposition (Cat-CVD) Method

Low temperature polycrystalline silicon: a review on deposition, physical properties and solar cell applications

Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced. This paper presents a comprehensive analytical treatment of ICs with multiple Si layers (3-D ICs). It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs with vertical inter-layer interconnects (VILICs). This analysis is based on dividing a chip into separate blocks, each occupying a separate physical level. A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis. Furthermore, thermal analysis of ICs with two Si layers is presented. It is demonstrated that using a thermally responsible design and/or a high-performance heat sinking technology, die temperatures for ICs with two Si layers can be reduced well below present die temperatures. Finally, implications of 3-D architecture on several circuit designs are also discussed.

http://eda.ee.ucla.edu/EE201A-04Spring/3D-overview.pdf

Multiple Si layer ICs: motivation, performance analysis, and design implications

Amongst alternative energy sources, photovoltaics hold a considerable promise for it is a plentiful, easily accessible and renewable source of power. Yet, the overall cost of generating electricity using the most advanced silicon based solar cells remains high compared to both traditional and other renewable power generation approaches. Organic thin film photovoltaics are an emerging economically competitive photovoltaic technology that combines manufacturing adaptability, low-cost processing and a lightweight, flexible device end-product. At present, however, commercial use of organic photovoltaics is hindered by low conversion efficiency and poor overall stability of the devices. Encapsulation with high barrier performance materials and structures is one of the key ways to address these issues and improve device lifetime. This paper will briefly outline the current understanding of the major degradation mechanisms, their interrelation and the internal and external factors that initiate these processes. Then, the paper will provide an overview of currently available encapsulant materials, their utility in limiting chemical (water vapor and oxygen penetration) and mechanical degradation within individual layers and device as a whole, and potential drawbacks to their application in organic photovoltaic devices.

Materials and methods for encapsulation of OPV: A review

A method for crystallizing amorphous silicon (a-Si) films at low temperatures is proposed. In the method, a-Si films are crystallized at temperatures lower than 400 °C by annealing in the presence of atomic hydrogen. The hydrogen atoms are generated by catalytic cracking reaction of H2 gas on a heated tungsten catalyzer in the catalytic chemical vapor deposition apparatus. It is found that the crystalline fraction of such an a-Si film is increased from 0% to several tens %, and at the same time the a-Si film itself is etched with the rate of several tens nm/min by annealing in atomic hydrogen. This increment of crystalline fraction appears dependent on the quality of initial a-Si films. It is implied that there are several types of a-Si even if the difference among a-Si films cannot be detected by Raman scattering spectroscopy and other means for measurements.

Low-temperature crystallization of amorphous silicon using atomic hydrogen generated by catalytic reaction on heated tungsten

Cat-CVD SiN passivation films for OLEDs and packaging

Silicon nitride (SiNx) films on Si and poly(ethylene terephthalate) (PET) substrates were prepared at approximately 150°C by catalytic chemical vapor deposition (Cat-CVD), using a SiH4/NH3 gas mixture. A water vapor transmission rate as low as 0.2 g/m2day and an O2 gas transmission rate of 0.6 cm3/m2day were achieved for a stoichiometric Si3N4 film of 77 nm thickness. Although these transmission rates depended on N/Si ratio, no optical absorption was observed under preferable deposition conditions.

http://iopscience.iop.org/article/10.1143/JJAP.43.L1362/pdf

Highly Moisture-Resistive SiNx Films Prepared by Catalytic Chemical Vapor Deposition

The influence of laser plasma soft X-ray (LPX) irradiation on crystallization of a-Si film by infrared (IR) furnace annealing is investigated. The crystallization temperature by LPX irradiation followed by IR annealing is lowered down to 420°C and the grain size increases up to 270 nm. This phenomenon is related with the change in characteristics of a-Si film which is generated by the bond distortion and relaxation during the LPX irradiation. It was found that the LPX-irradiated film is constituted by the two different layers and the refractive index of upper layer was lower than that of under layer. The dangling bond density of a-Si film was also decreased by LPX irradiation to a-Si film. From these results, the crystallization mechanism is discussed.

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Akira Heya

Papers

Low-temperature crystallization of amorphous silicon using atomic hydrogen generated by catalytic reaction on heated tungsten

Cat-CVD SiN passivation films for OLEDs and packaging

Highly Moisture-Resistive SiNx Films Prepared by Catalytic Chemical Vapor Deposition

Influence of Laser Plasma Soft X-Ray Irradiation on Crystallization of a-Si Film by Infrared Furnace Annealing

Low-temperature crystallization of amorphous silicon and amorphous germanium by soft X-ray irradiation