Showing papers by "Alberto Sangiovanni-Vincentelli published in 1989"

Logic synthesis for vlsi design

Abstract: Very Large Scale Integration (scVLSI) currently allows hundreds of thousands of transistors in a single application-specific integrated circuit. The trend of increasing levels of integration has stressed the ability of the designer to keep pace. Traditional integrated circuit design has relied on analysis tools to measure the quality and correctness of a circuit before fabrication. However, only recently have synthesis tools been used to assist in the design process. The advantages of automatic synthesis include reduced design time, reduced probability of design error, and higher quality designs because more effort is focused at higher-levels in the design. Automatic placement and routing, a form of physical design synthesis, has become widely accepted over the last five years; however, logic design has, for the most part, remained a manual task. Logic synthesis is the automation of the logic design phase of scVLSI design; that is, choosing the specific gates and their interconnection to build a desired function. For digital integrated circuits which are partitioned into control and data-path portions, design of the control logic is often the most time-consuming. It is generally on the critical path for timing, and, because of the complexity of producing a correct description of the control, it is often on the critical path for completion of the design. Therefore, tools to assist in logic design will have a large impact on the design of integrated circuits. However, the benefits of automatic logic design are lost if the result does not meet its area, speed, or power constraints. Therefore, a critical aspect of automatic logic synthesis is the optimization problem of deriving a high-quality design from an initial specification. This thesis provides a set of logic optimization algorithms which together form a complete system for logic synthesis in a scVLSI design environment. Efficient, optimal algorithms are proposed for two-level minimization, multiple-level decomposition, and technology mapping. The techniques described in this thesis have been implemented in a software program called scMIS. The design of a complex digital circuit is included as part of this thesis to demonstrate the application of logic synthesis to a realistic design problem.

A synthesis and optimization procedure for fully and easily testable sequential machines

Abstract: The authors outline a synthesis procedure which beginning from a state transition graph (STG) description of a sequential machine produces an optimized fully and easily testable logic implementation. This logic-level implementation is guaranteed to be testable for all single stuck-at faults in the combinational logic and the test sequences for these faults can be obtained using combinational test generation techniques alone. The sequential machine is assumed to have a reset state and be R-reachable. All single stuck-at faults in the combinational logic and the input and output stuck-at faults of the memory elements in the synthesized logic-level automaton can be tested without access to the memory elements using these test sequences. Thus this procedure represents an alternative to a scan design methodology. The area penalty incurred due to the constraints on the optimization are small. The performance of the synthesized design is usually better than that of an unconstrained design optimized for area alone. The authors show that an intimate relationship exists between state assignment and the testability of a sequential machine. They propose a procedure of constrained state assignment and logic optimization which guarantees testability for both Moore and Mealy machines. >

NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations

Abstract: The problem of encoding the states of a synchronous Finite State Machine (FSM), so that the area of a two-level implementation of the combinational logic is minimized, is addressed. As in previous approaches, the problem is reduced to the solution of the combinatorial optimization problems defined by the translation of the cover obtained by a multiple-valued logic minimization or by a symbolic minimization into a compatible boolean representation. In this paper we present algorithms for their solution, based on a new theoretical framework that offers advantages over previous approaches to develop effective heuristics. The algorithms are part of NOVA, a program for optimal encoding of control logic. Final areas averaging 20% less than other state assignment programs and 30% less than the best random solutions have been obtained. Literal counts averaging 30% less than the best random solutions have been obtained.

Multi-Level Logic Simplification Using Don't Cares and Filters

Abstract: Simplification of a multi-level network is used to perform form transformations on parts of the network to obtain an alternate structure that is optimal with respect to area. A technique for obtaining such an optimal structure involves the use of two-level logic minimization on the components of the multi-level logic network. At each component, the structure of the network is captured by intermediate and fan-out don't care sets, which are utilized in the two-level minimization. However, the generation of all the don't cares yield very large sets for most networks and consequently the complete minimization of the components of the circuits require a very large amount of computer time. In this paper we describe algorithms to reduce the size of the don't care sets, so that only the portions that will be useful in minimization at each component of the circuit are retained. We develop both an exact filter and a heuristic filter that prove to be very effective for a large set of benchmark examples. Results show that our technique achieves the same quality as that obtained by doing complete minimizations at each component of the circuits but in much shorter time. This new approach to simplification of multi-level networks has been incorporated into the MIS (version 2.1) logic synthesis system.

Boolean decomposition in multilevel logic optimization

Abstract: Algorithms are presented for Boolean decomposition, which can be used to decompose a programmable logic array (PLA) into a set of smaller interconnected PLAs such that the overall area of the resulting logic network, deemed to be the sum of the areas of the constituent PLAs, is minimized. These algorithms can also be used to identify good Boolean factors which can be used as strong divisors during the logic optimization to reduce the literal counts/area of general multilevel logic networks. Excellent results have been obtained. >

A mixed frequency-time approach for distortion analysis of switching filter circuits

Abstract: A new efficient mixed frequency-time approach to computing steady-state and intermodulation distortion of switching filters without resorting to macromodeling or the slow-clock approach has been presented The method works by computing the solution to the differential equation system associated with a circuit for only J clock cycles, where J is the number of coefficients needed in the Fourier series to represent accurately the sequence of initial points in each clock cycle Thus this method is particularly efficient when the number of coefficients in the Fourier series is many fewer than the number of clock cycles in one input signal period >

ORCA A Sea-of-gates Place and Route System

Abstract: Sea-of-gates is becoming an important design style for Application Specific Integrated Circuits (ASICs). The sea-of-gates technology offers more flexible placement and routing options not available in gate arrays. Very few systems are available today that can automatically layout sea-of-gates and none of these systems effectively use the features available in sea-of-gates architecture. ORCA is a place and route system for sea-of-gates, whose objective is to produce the highest density layout by fully exploiting the inherent features of this new design style. The ORCA system starts with a module generator which preprocesses memory arrays and other logic with a regular structure to form high density macros. The remaining logic is clustered together to form flexible macros, which we call porous. The porous macro-cells allow global routing to pass through the macro instead of detouring around its perimeter. The porous macros are dynamically shaped and resized by interaction with global wiring analysis. Finally, a general channelless area router has been developed to address the multiple layers of interconnect and routing areas which will be dominantly over-the-cell. Due to the large size of the problem (e.g. 100,000 gates), the placement and routing algorithms are hierarchical.

Timing Analysis in a Logic Synthesis Environment

Abstract: A goal of a logic synthesis system is the automatic generation of area optimised designs that meet timing requirements. The design process involves repeated timing analyses followed by appropriate modifications. We present fast new algorithms for system level timing analysis and for the generation of timing constraints to guide the re-design of portions of combinational logic. Our systematic approach correctly models designs that incorporate level sensitive latches controlled by multi-frequency, as well as simple multi-phase, clocks. A new feature is that the minimum number of settling times are evaluated for the nodes of combinational networks with input transitions controlled by different clock signals. The computer program Hummingbird uses the algorithms presented. Hummingbird interfaces with other programs in the Berkeley Synthesis System through the OCT data base. For a digital signal processing chip, comprising 3681 standard cells, timing analysis is performed in 14.87 cpu seconds on a VAX 8800 running the ULTRIX operating system.

Logic verification algorithms and their parallel implementation

Abstract: LOgic VERification (LOVER) incorporates a novel approach to combinational logic verification and obtains excellent results when compared to existing techniques. The authors describe a new verification algorithm, LOVER-PODEM, whose enumeration phase is based on PODEM. A variant of LOVER-PODEM, called PLOVER, is presented. Parallel logic verification schemes have been developed for the first time. Issues in efficiently parallelizing both general and specific LOVER-based approaches to logic verification over a large number of processors are addressed. The parallelism inherent in the LOVER framework regardless of what enumeration and simulation algorithms are used is discussed. Since the enumeration phase is the efficiency bottleneck in parallelizing LOVER-based approaches, parallel versions of PODEM-based enumeration algorithms have been developed. >

Logic minimization for factored forms

Abstract: The minimization of Boolean functions is usually aimed at obtaining a minimum sum-of-products representation, measured in terms of the number of product terms produced. In multilevel logic, however, a better objective function is a minimized factored form. Traditionally, logic functions have been factored by using algebraic techniques on a minimized sum-of-products. Algebraic factorization techniques explore only part of the solution space. A technique for factoring based on Boolean operations is presented. This technique often leads to a better factored form for a logic function. The algorithm uses the Boolean operations which are the basis of the two-level minimizer ESPRESSO. The technique has been implemented in the multilevel logic minimization program MIS. Some results of Boolean factorization of individual nodes in multilevel networks are presented and then compared with other factoring methods in MIS. >