Alexandre Joannou

TL;DR: This document describes the rapidly maturing design for the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA), and provides reference documentation for the CHERI instruction-set architecture and potential memory models, along with their requirements.

TL;DR: The cache behavior of an in-memory tag table is characterized and it is demonstrated that an optimized implementation can typically achieve a near-zero memory traffic overhead.

TL;DR: This work describes the first adaptation of a full C-language operating system (FreeBSD) with an enterprise database (PostgreSQL) for complete spatial and referential memory safety and shows that awareness of abstract capabilities, coupled with CHERI architectural capabilities, can provide more complete protection, strong compatibility, and acceptable performance overhead compared with the pre-CHERI baseline and software-only approaches.

TL;DR: It is measured a 50 to 75 percent reduction in L2 misses for many compiled C-language benchmarks running under a commodity operating system using compressed 128-bit and 64-bit formats, demonstrating both compatibility with and increased performance over the uncompressed, 256-bit format.

TL;DR: ISA support for sealed capabilities, hardware-assisted checking during protection-domain switching, a lightweight capability flow-control model, and fast register clearing are proposed, while retaining the flexibility of a software-defined protection- domain transition model.