John Baldwin

TL;DR: This document describes the rapidly maturing design for the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA), and provides reference documentation for the CHERI instruction-set architecture and potential memory models, along with their requirements.

TL;DR: The cache behavior of an in-memory tag table is characterized and it is demonstrated that an optimized implementation can typically achieve a near-zero memory traffic overhead.

TL;DR: This work describes the first adaptation of a full C-language operating system (FreeBSD) with an enterprise database (PostgreSQL) for complete spatial and referential memory safety and shows that awareness of abstract capabilities, coupled with CHERI architectural capabilities, can provide more complete protection, strong compatibility, and acceptable performance overhead compared with the pre-CHERI baseline and software-only approaches.

TL;DR: Cornucopia is a lightweight capability revocation system for CHERI that implements non-probabilistic C/C++ temporal memory safety for standard heap allocations and extends the CheriBSD virtual-memory subsystem to track capability flow through memory and provides a concurrent kernel-resident revocation service that is amenable to multi-processor and hardware acceleration.

TL;DR: The Capability Hardware Enhanced RISC Instructions (CHERI) instruction set architecture as discussed by the authors has been developed by SRI International and the University of Cambridge to address known performance and robustness gaps in commodity ISAs.