International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

http://ieeexplore.ieee.org/iel5/5/31324/01456901.pdf

Microelectronic circuits

Injection-locked oscillators divide at very high frequencies and consume low power. They are not widely deployed in commercial products because they operate over small, often unpredictable, ranges of input frequencies. Ring oscillators as dividers are interesting because they are compact, and capable of a multi-phase output, including quadrature phases. Using a generalized Adler's equation for large injections, we analyze the operation of injection-locked ring oscillators and derive expressions for the input lock range. We discover that injection in the correct progressive phases greatly widens the lock range; all that is needed is the right delay cell circuit, and the injection input in one or two phases. As proof of concept, divide-by-two and six prototypes are built. The measured lock range spans DC to 1.5 the free-running frequency, the highest reported to date.

Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers

Ultra-short- and short-reach optical interconnects are the new high growth applications for optical communications. High capacity density, high spectral efficiency, low cost, low power consumption, and fast configurability are some of the key requirements for potential optical transmission technology candidates. Based on recent progress in orbital angular momentum multiplexed optical transmission and optical device technologies, this paper discusses the potentials and challenges of using orbital angular momentum multiplexing in optical interconnect applications scenarios to meet above requirements.

Potentials and challenges of using orbital angular momentum communications in optical interconnects.

Networks-on-chip (NoC) have emerged to tackle different on-chip communication challenges and can satisfy different demands in terms of performance, cost and reliability. Currently, interconnects based on metal are reaching performance limits given relentless technology scaling. In particular, a performance bottleneck has emerged due to the demands for communication in terms of bandwidth for multicasting and broadcasting. As a result, various state-of-the-art architectures have been proposed as alternatives and emerging interconnects including the use of optics or radio frequency (RF). This article presents a comprehensive survey of these various interconnect fabrics, and discusses their current and future potentials and obstacles as well. This article aims to drive the research community to achieve a better utilization of the merits of on-chip interconnects and addresses the challenges involved. New interconnect technologies, such as optical interconnect, wireless NoC (WiNoC), RF transmission lines (RF-I) and surface wave interconnects (SWI), are discussed, evaluated and compared. Consequently, these emerging interconnects can continue to provide the cost efficiency and performance that are highly demanded for future many-core processors and high performance computing.

/pdf/a-survey-of-emerging-interconnects-for-on-chip-efficient-5azmkoa9is.pdf

A Survey of Emerging Interconnects for On-Chip Efficient Multicast and Broadcast in Many-Cores

Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra- and inter-chip interconnect technologies. Optical interconnect is a promising long term solution. However, while significant progress in optical signaling has been made in recent years, networking issues for on-chip optical interconnect still require much investigation. Taking the underlying optical signaling systems as a drop-in replacement for conventional electrical signaling while maintaining conventional packet-switching architectures is unlikely to realize the full potential of optical interconnects. In this paper, we propose and study the design of a fully distributed interconnect architecture based on free-space optics. The architecture leverages a suite of newly-developed or emerging devices, circuits, and optics technologies. The interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.

/pdf/an-intra-chip-free-space-optical-interconnect-3lhqdkur4a.pdf

An intra-chip free-space optical interconnect

Optimizing the common case has been an adage in decades of processor design practices. However, as the system complexity and optimization techniquespsila sophistication have increased substantially, maintaining correctness under all situations, however unlikely, is contributing to the necessity of extra conservatism in all layers of the system design. The mounting process, voltage, and temperature variation concerns further add to the conservatism in setting operating parameters. Excessive conservatism in turn hurt performance and efficiency in the common case. However, much of the systempsilas complexity comes from advanced performance features and may not compromise the whole systempsilas functionality and correctness even if some components are imperfect and introduce occasional errors. We propose to separate performance goals from the correctness goal using an explicitly-decoupled architecture. In this paper, we discuss one such incarnation where an independent core serves as an optimistic performance enhancement engine that helps accelerate the correctness-guaranteeing core by passing high-quality predictions and performing accurate prefetching. The lack of concern for correctness in the optimistic core allows us to optimize its execution in a more effective fashion than possible in optimizing a monolithic core with correctness requirements. We show that such a decoupled design allows significant optimization benefits and is much less sensitive to conservatism applied in the correctness domain.

A performance-correctness explicitly-decoupled architecture

We propose injection-locked clocking (ILC) to combat deteriorating clock skew and jitter, and reduce power consumption in high-performance microprocessors. In the new clocking scheme, injection-locked oscillators are used as local clock receivers. Compared to conventional clocking with buffered trees or grids, ILC can achieve better power efficiency, lower jitter, and much simpler skew compensation thanks to its built-in deskewing capability. Unlike other alternatives, ILC is fully compatible with conventional clock distribution networks. In this paper, a quantitative study based on circuit and microarchitectural-level simulations is performed. Alpha21264 is used as the baseline processor, and is scaled to 0.13 m and 3 GHz. Simulations show 20- and 23-ps jitter reduction, 10.1% and 17% power savings in two ILC configurations. A test chip distributing 5-GHz clock is implemented in a standard 0.18- m CMOS technology and achieved excellent jitter performance and a deskew range up to 80 ps.

Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors

This letter presents a new optical interconnect system for intrachip communications based on free-space optics. It provides all-to-all direct communications using dedicated lasers and photodetectors, hence avoiding packet switching while offering ultra-low latency and scalable bandwidth. A technology demonstration prototype is built on a circuit board using fabricated germanium photodetectors, micro-lenses, commercial vertical-cavity surface-emitting lasers, and micro-mirrors. Transmission loss in an optical link of 10-mm distance and crosstalk between two adjacent links are measured as 5 and -26 dB, respectively. The measured small-signal bandwidth of the link is 10 GHz.

/pdf/a-3-d-integrated-intrachip-free-space-optical-interconnect-2amghgut98.pdf

A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips

An efficient mechanism to track and enforce memory dependences is crucial to an out-of-order microprocessor. The conventional approach of using cross-checked load queue and store queue, while very effective in earlier processor incarnations, suffers from scalability problems in modern high-frequency designs that rely on buffering many in-flight instructions to exploit instruction-level parallelism. In this paper, we make a case for a very different approach to dynamic memory disambiguation. We move away from the conventional exact disambiguation strategy and adopt an opportunistic method: we allow loads and stores to access an L0 cache as they are issued out of program order, hoping that with such a laissez-faire approach, most loads actually obtain the right value. To guarantee correctness, they execute a second time in program order to access the nonspeculative L1 cache. A discrepancy between the two executions triggers a replay. Such a design completely eliminates the necessity of real-time violation detection and thus avoids the conventional approach's complexity and the associated scalability issue. We show that even a simplistic design can provide similar performance level achieved with a conventional queue-based approach with optimisticallysized queues. When simple, optional optimizations are applied, the performance level is close to that achieved with ideally-sized queues.

Alok Garg

Papers

An intra-chip free-space optical interconnect

A performance-correctness explicitly-decoupled architecture

Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors

A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips

Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification