This letter presents a new low-dropout regulator (LDO) architecture based on an active capacitor. The active capacitor located at the LDO output helps reduce both output variation and settling time under load step changes without using any passive capacitor. A transient-enhanced control loop is also established to further improve the transient performances and significantly lower the quiescent current. Implemented in a standard 180-nm CMOS process, the proposed LDO only consumes a no-load quiescent current of 340 nA to support a maximum load of 80 mA. With only a 3-pF compensation capacitor, the proposed LDO is stable over a wide range of the capacitive load from 0 to 600 pF. The proposed LDO also demonstrates a fast transient response to a 79.9-mA/100-ns load step with the settling time of 110 ns and a voltage droop of 120 mV. Compared to the prior art, this work achieves the best transient FOM of 0.02 fs.

A 340-nA-Quiescent 80-mA-Load 0.02-fs-FOM Active-Capacitor-Based Low-Dropout Regulator in Standard 0.18- μ m CMOS

This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor. Starting from a typical LDO topology, an error amplifier (EA) that drives a PMOS pass transistor and a passive feedback network, we inserted a novel circuit, with the input AC-coupled to the LDO output and the output connected directly to the pass transistor gate. This circuit creates an inner feedback loop able to react quicker than the main feedback loop to variations in the output voltage, and appropriately inject or sink current to/from the gate node. Moreover, the inner feedback loop helps reduce the equivalent small-signal impedance at the LDO output, which in turn reduces the impact the pole associated with the output node has on the LDO stability. A compact circuit implementation of this topology is presented in this paper: it combines the proposed fast transient & frequency compensation circuit with a high slew-rate EA. The resulting LDO was integrated in a 130 nm standard CMOS technology. The measurement results are in good agreement with simulations and validate the concept and design. The LDO provides a steady 1 V output with the supply voltage varying from 1.2 V to 1.5 V and the load current going up to 100 mA. Its fast response to load transients helps maintain the output voltage overshoot and undershoot below 250 mV for CL = 0 and under 60 mV for <inline-formula> <tex-math notation="LaTeX">$\text{C}_{\mathrm {L}} =1\,\,\mu \text{F}$ </tex-math></inline-formula>, when the load current varies between 1 <inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> and 100 mA in 1 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>. The LDO requires only 6.2 <inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> of quiescent current and occupies 0.018 mm2 of die area.

https://ieeexplore.ieee.org/ielx7/6287639/9668973/09681807.pdf

Fast LDO Handles a Wide Range of Load Currents and Load Capacitors, up to 100 mA and Over 1μF

This paper presents a low power fast transient low-dropout regulator (LDO) employing a Super Class-AB operational transconductance amplifier (OTA). The proposed structure not only achieve large charging/discharging current at the gate of power transistor but also a gain factor, which not only shows excellent transient performance but also ensures enough line/load regulation. Without adding addition circuit structure, the proposed LDO demonstrates a comprehensive improvement, including enhanced line/load regulation and transient performance, when compared with conventional counterpart, implemented in 0.18 μ m CMOS technology, the proposed LDO shows a transient voltage variation of 53 mV at Vout for a load step of 10 μ A -200 mA and possesses a line/load regulation of 1.25 mV/V and 100 μ V /mA respectively.

A Fast-Transient low-dropout regulator (LDO) With Super Class-AB OTA

This paper presents a low power fast transient low-dropout regulator (LDO) employing a Super Class-AB operational transconductance amplifier (OTA). The proposed structure not only achieve large charging/discharging current at the gate of power transistor but also a gain factor, which not only shows excellent transient performance but also ensures enough line/load regulation. Without adding addition circuit structure, the proposed LDO demonstrates a comprehensive improvement, including enhanced line/load regulation and transient performance, when compared with conventional counterpart, implemented in 0.18 μ m CMOS technology, the proposed LDO shows a transient voltage variation of 53 mV at Vout for a load step of 10 μ A -200 mA and possesses a line/load regulation of 1.25 mV/V and 100 μ V /mA respectively. 

A fast-transient low-dropout regulator (LDO) with Super Class-AB OTA

This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor. Starting from a typical LDO topology, an error amplifier (EA) that drives a PMOS pass transistor and a passive feedback network, we inserted a novel circuit, with the input AC-coupled to the LDO output and the output connected directly to the pass transistor gate. This circuit creates an inner feedback loop able to react quicker than the main feedback loop to variations in the output voltage, and appropriately inject or sink current to/from the gate node. Moreover, the inner feedback loop helps reduce the equivalent small-signal impedance at the LDO output, which in turn reduces the impact the pole associated with the output node has on the LDO stability. A compact circuit implementation of this topology is presented in this paper: it combines the proposed fast transient & frequency compensation circuit with a high slew-rate EA. The resulting LDO was integrated in a 130 nm standard CMOS technology. The measurement results are in good agreement with simulations and validate the concept and design. The LDO provides a steady 1 V output with the supply voltage varying from 1.2 V to 1.5 V and the load current going up to 100 mA. Its fast response to load transients helps maintain the output voltage overshoot and undershoot below 250 mV for C L = 0 and under 60 mV for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{C}_{\mathrm {L}} =1\,\,\mu \text{F}$ </tex-math></inline-formula> , when the load current varies between 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> and 100 mA in 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> . The LDO requires only 6.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> of quiescent current and occupies 0.018 mm 2 of die area.

This article proposes an LDO with fast response to load transients that can handle any practical capacitive loads. These features are mainly due to a novel frequency compensation circuit tailored for its error amplifier, which is based on an improved version of the popular common gate amplifier. A simple yet effective approach to the small-signal analysis of LDO with multiple feedback loops is employed to analyse intuitively the LDO and derive key design constraints. Simulation and measurement results performed on a test chip implemented in standard 130nm CMOS process validated the proposed LDO. It requires only $0.7\mu \text{A}$ quiescent current but exhibits an excellent response to load transients: when the load current jumps from 0A to 100mA in $1\mu \text{s}$ the output voltage presents an undershoot of 76mV and an overshoot of 198mV, without decoupling capacitors. It compares well against seven LDOs designed with common gate error amplifiers for similar levels of supply voltage, output voltage and current and against seven fast LDOs employing different error amplifiers. A figure-of-merit that considers the quiescent current, the maximum load current and capacitance, as well as the output voltage deviation, yielded a value for our LDO 39.8 times better than for the nearer competitor that employs common gate amplifier and 6 times better than the one employing a different error amplifier. When considering edge time and process scaling the performance of the proposed LDO is 4.8, respectively 4.5, times better than the second best in both comparisons.

/pdf/ldo-with-improved-common-gate-class-ab-ota-handles-any-load-4v8g5lg3kb.pdf

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

This paper presents a design methodology based on electro-thermal simulations for the over-temperature protection (OTP) of low drop-out voltage regulators (LDO). The OTP monitors the die temperature developed within the LDO and shuts down the circuit when the temperature reaches a set maximum level (the OTP trigger point). The proposed methodology involves running iteratively electrical, thermal and electro-thermal simulations. It addresses two major issues: first, it allows the designer to identify the suitable location of the OTP sensor by considering the temperature distribution within the LDO's power-stage. Second, the OTP trigger point can be set accurately taking into account coupled electro-thermal phenomena, so that the circuit is shut down when any section of the die reaches the maximum allowable temperature. The proposed methodology is validated by measurements performed on an LDO designed using it.

Andrei Negoita

Papers

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Design methodology for over-temperature protection of an LDO voltage regulator by using electro-thermal simulations

Design methodology for over-temperature and over-current protection of an LDO voltage regulator by using electro-thermal simulations