A
Anees Ullah
Researcher at University of Engineering and Technology, Peshawar
Publications - 38
Citations - 344
Anees Ullah is an academic researcher from University of Engineering and Technology, Peshawar. The author has contributed to research in topics: Field-programmable gate array & Control reconfiguration. The author has an hindex of 8, co-authored 31 publications receiving 213 citations. Previous affiliations of Anees Ullah include City University of Science and Information Technology & Case Western Reserve University.
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Comparison Based Analysis of Different Cryptographic and Encryption Techniques Using Message Authentication Code (MAC) in Wireless Sensor Networks (WSN)
Sadaqat Ur Rehman,Muhammad Bilal,Basharat Ahmad,Khawaja Muhammad Yahya,Anees Ullah,Obaid Ur Rehman +5 more
TL;DR: This research work investigates different cryptographic techniques, and provides efficient techniques for communicating device, by selecting different comparison matrices that satisfies both the security and restricted resources in WSN environment.
Proceedings ArticleDOI
An error-detection and self-repairing method for dynamically and partially reconfigurable systems
TL;DR: This paper proposes a self-repairing method for partially and dynamically reconfigurable systems applied at a fine-grain granularity level that is able to detect correct and recover errors using the run-time capabilities offered by modern SRAM-based FPGAs.
Proceedings ArticleDOI
On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs
Luca Sterpone,Anees Ullah +1 more
TL;DR: This work proposes a novel circuit instrumentation method for probing Triple Modular Redundancy (TMR) circuits for error detection at the granularity of individual domains and then use selective run-time dynamic reconfiguration for recovery.
Journal ArticleDOI
PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration
TL;DR: The proposed scheme is based on the use of lookup tables (LUTs) and partial reconfiguration to achieve a more effective use of the FPGA resources while supporting the addition and removal of rules.
Journal ArticleDOI
Error Detection and Correction in SRAM Emulated TCAMs
TL;DR: Protection of the memories used to emulate TCAMs is considered and it is shown that by exploiting the fact that only a subset of the possible memory contents are valid, most single-bit errors can be corrected when the memories are protected with a parity bit.