A
Anees Ullah
Researcher at University of Engineering and Technology, Peshawar
Publications - 38
Citations - 344
Anees Ullah is an academic researcher from University of Engineering and Technology, Peshawar. The author has contributed to research in topics: Field-programmable gate array & Control reconfiguration. The author has an hindex of 8, co-authored 31 publications receiving 213 citations. Previous affiliations of Anees Ullah include City University of Science and Information Technology & Case Western Reserve University.
Papers
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Journal ArticleDOI
Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory
TL;DR: A fault detection and location scheme is proposed based on partial reencoding for the faults in the user memory of the RS-EC decoder and theoretical analysis shows that the scheme could detect most faults with small missing and false detection probability.
Journal ArticleDOI
VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC
Bushra Sultana,Anees Ullah,Arsalan Ali Malik,Ali Zahir,Pedro Reviriego,Fahad Bin Muslim,Nasim Ullah,Waleed Ahmad +7 more
TL;DR: An internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented and achieves competitive resource utilization when compared to existing approaches.
Journal ArticleDOI
An innovative user-friendly platform for Covid-19 pandemic databases and resources.
Shahid Ullah,Anees Ullah,Wajeeha Rahman,Farhan Ullah,Sher Bahadar Khan,Gulzar Ahmad,Muhammad Ijaz,Tianshun Gao +7 more
TL;DR: The COVID-19 pandemic database (CO-19 PDB) as mentioned in this paper aims to provide wonderful insights for COVID19 researchers with the well-gathered of all the COVID2019 data to one platform, which is a global challenge for the research community.
Journal ArticleDOI
A novel tool-flow for zero-overhead Cross-Domain Error resilient partially reconfigurable X-TMR for SRAM-based FPGAs
TL;DR: This work proposes a TMR architecture that exploits the fracturable nature of Look Up Tables for simultaneously mapping of majority-voting and error detection at the granularity of TMR domains and demonstrates significant reduction in repairing times along with better resilience to cross-domain errors with zero hardware overhead.
Proceedings ArticleDOI
FlexTCAM: Beyond Memory Based TCAM Emulation on FPGAs
TL;DR: In this paper, it is shown that FPGA emulated TCAMs are actually more powerful than traditional TCAM and can support more generic rules, making them more efficient in some applications as the number of rules needed to implement a system can be significantly reduced.