Thermal management and temperature uniformity enhancement of electronic devices by micro heat sinks: A review

Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through -silicon - vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.

A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems

Sectional oblique fins are employed, in contrast to continuous fins, in order to modulate the flow in a microchannel heat sink. The breakage of continuous fin into oblique sections leads to reinitialization of boundary layers and generation of secondary flows that significantly enhance the cooling performance of the heat sink. In addition, an oblique finned microchannel heat sink has the flexibility to tailor local heat transfer performance by varying its oblique fin pitch. Clusters of oblique fins at higher density can be created in order to promote a greater degree of boundary layer redevelopment and secondary flow generation to provide more effective cooling at the high heat-flux region. Thus, the variation of oblique fin pitch can be exploited for hotspot mitigation. Experimental studies of a silicon chip with two hotspot scenarios show that the temperature hike and the temperature difference for the enhanced microchannel heat sink with variable pitch are reduced by as much as 17.1 °C and 15.4 °C, respectively. As a result, temperature distribution across the silicon chip is more uniform. In addition, the associated pressure drop penalty is much smaller than the achieved heat transfer enhancement, rendering it as an effective hotspot mitigating strategy for the single-phase microchannel heat sink.

Hotspot Mitigating With Obliquely Finned Microchannel Heat Sink—An Experimental Study

The effects of substrate roughness on the wettability of non-reactive wetting and compound forming wetting systems were investigated by the sessile drop technique at high temperature. The AgCu eutectic alloy/copper and the AgCuTi/alumina wetting systems were selected. It is found that the substrate roughness has a great effect on both wetting systems. For the non-reactive wetting system, an additional capillary driving force exists when melt flows into the micro v-grooves of the rough surface, leading to a decrease in final contact angle (θf) and consequently a better wettability. For the compound forming metal/ceramic reactive wetting system, wetting on a rough surface exhibits a slow spreading kinetics and a short period of spreading time, and the retarding force of spreading increases because of overcoming the energy barriers due to asperities of the rough surface, resulting in an increase in θf. Thus, a rough substrate has negative effect on the wettability of the compound forming reactive wetting system.

Effects of roughness on the wettability of high temperature wetting system

Wetting and spreading in high temperature reactive metal-metal systems is of significant importance in many joining processes. An overview of reactive wetting is presented outlining the principal differences between inert and reactive wetting. New experimental evidence is presented that identifies an early time regime in reactive wetting in which spreading occurs without macroscopic morphological change of the solid-liquid interface. This regime precedes the heavily studied reactive wetting regime. Additional new experimental evidence is presented of kinetic roughening in a high temperature reactive system. Quantitative characterization of this roughening reveals similarities with room temperature systems. These new data provide evidence that supports the existence of several sequential time regimes in the reactive wetting process in which different physicochemical phenomena are dominant.

https://iopscience.iop.org/article/10.1088/0953-8984/21/46/464130/pdf

Reactive wetting in metal-metal systems.

Reactive wetting in metal–metal systems involves complex interactions between the molten phase and the solid substrate. The simplest interaction involves only the dissolution of the substrate into the molten phase. The more complex interaction involves both dissolution of the substrate and compound formation at the solid–liquid boundary. The fundamental differences between these two types of reactive wetting are identified by studying the purely dissolutive system Bi–Sn and the compound-forming system Au–Sn. Experiments employ the traditional sessile drop technique as well as a novel two-dimensional drop transfer technique that enables real-time visualization of the solid–liquid interface evolution. Recent results from wetting of pure Sn on Au-coated Cu substrates are also presented and reveal a much richer wetting behavior than either Sn on Au or Sn on Cu binary systems.

Reactive wetting in metal/metal systems : Dissolutive versus compound-forming systems

The placement and arrangement of the different components on a microprocessor chip is examined to mitigate the hot spots that may arise on the device during its operation. The power dissipation of the individual components on a microprocessor is spatially and temporally non-uniform, possibly resulting in high thermal gradients and, as a consequence, high thermal stresses. These hot spots arise because the power dissipated by some components accounts for a major fraction of the total power of the device. The device then develops large temperature gradients and localized hot spots. These hot spots can cause device failures and a loss in performance that results when the clock frequency slows with voltage scaling to cope with thermal emergencies. It can also lead to lower yield.

Hot spot mitigation using single-phase microchannel cooling for microprocessors

The spatial and temporal non-uniform power of the microprocessor components endangers its functionality and reliability. The rapid change in dynamic power affects electric circuitry, leads to electron migration and high leakage currents; all of which contribute to localized hot spots and high thermal stresses. Though, the dynamic thermal management techniques (DTM) keep the chip temperature within the thermal budget but their efficacy depends on the accurate measurement of the emerging hot spot temperature. The time lag between the peak power input to the microprocessor components and the corresponding hot spot on its surface is therefore a critical parameter for the effective application of DTM techniques. This paper analyses the dynamic power of the microprocessor components to estimate the thermal time lag of the hot spot. The real power estimates of an Intel P4 processor are collected for selected benchmarks, analyzed and then supplied to the numerical model for thermal analysis. In all the benchmarks, the component contributing to hot spot had significantly high heat flux compared to the remaining components of the processor. The power data of the hot component showed periodic peaks of high power which raises the hot spot temperature beyond working limits. The time lapse between peak power input to the time when hot spot temperature becomes 120°C, is defined as thermal time lag for our analysis. The knowledge of thermal time lag can be applied by DTM techniques to prevent the power overshoot in high heat flux components. The thermal time lag can also be exploited to boost the clock frequency repeatedly in cyclic fashion to realize high performance over an extended duration. This repeated boosting can be realized by ensuring that the safe temperature limits are not exceeded in each boosting period and with a sufficient cool-down interval between boosts.

Transient power analysis to estimate the thermal time lag of a microprocessor hot spot

The power dissipation in a microprocessor is spatially and temporally non-uniform resulting in hot spots, high temperature gradients and as a consequence, high thermal stresses. This temperature non-uniformity and existence of hotspots in the processor poses a threat to the performance and reliability of the processor in the long run. The dynamic thermal management (DTM) techniques applied at the architectural level are proven to be more efficient to address the rapid power variation in the processor components. Since, the efficiency of DTM techniques is based on the thermal response of the microprocessor, it is imperative to reduce the time lag between the thermal response of the chip and strategy adopted by DTM to manage the hotspot temperature. This strategy will also be applicable in boosting up the clock frequency momentarily for high performance without causing any chip damage due to high temperature excursions. This paper studies the temporal and spatial variation of power dissipation in a commercially available single-core microprocessor. The real power dissipation estimates are obtained for benchmarks using cycle-accurate microarchitectural simulator. In the selected benchmarks, the hottest component has significantly high power dissipation compared to remaining components of the processor. The real time power dissipation of the components is then analyzed to study the thermal time constant of the hotspot and the combined thermal effect of the other components on the hotspot temperature. The analysis is done both for a finer and coarser time intervals to identify the effect of time scale on the thermal time constants.

https://www.researchgate.net/profile/Anjali_Chauhan6/publication/261417422_Analysing_real_time_power_of_the_microprocessor_to_estimate_thermal_time_constant_of_the_hotspot/links/55d91f0708ae9d65948fa63e.pdf

Analysing real time power of the microprocessor to estimate thermal time constant of the hotspot

Solving Thermal Issues in a Three-Dimensional-Stacked-Quad-Core Processor by Microprocessor Floor Planning, Microchannel Cooling, and Insertion of Through-Silicon-Vias

Anjali Chauhan

Papers

Reactive wetting in metal/metal systems : Dissolutive versus compound-forming systems

Hot spot mitigation using single-phase microchannel cooling for microprocessors

Transient power analysis to estimate the thermal time lag of a microprocessor hot spot

Analysing real time power of the microprocessor to estimate thermal time constant of the hotspot

Solving Thermal Issues in a Three-Dimensional-Stacked-Quad-Core Processor by Microprocessor Floor Planning, Microchannel Cooling, and Insertion of Through-Silicon-Vias