In this paper, we have proposed dopingless gate all around (GAA) nanowire tunnel field-effect transistor (NWTFET) made up of dual-material channel (DMaC). Charge-plasma (CP) technique is used to induce the doping concentration of charge carriers in the intrinsic semiconductor. GAA structure uses zirconium silicate (IV) (ZrSiO4)/silicon dioxide (SiO2) for heterogeneous gate (HG) structure metalized with two different gate metals. Auxiliary gate (GM1) and tunneling gate (GM2) have different work functions, i.e., $\phi _{1}$ and $\phi _{2}$ . The device physics is analyzed using electric field, charge carrier concentration, energy-band diagram, and tunneling rate across the structure. The effect of variation in $\phi _{1}$ and $\phi _{2}$ helps in the analysis of the ambipolar and analog behavior of the proposed device CP-dual metal-HG-DMaC-NWTFET. The reported ON-state current is $5.54~\mu \text{A}/\mu \text{m}$ , and the OFF-state current is approximately 0.1 aA/ $\mu \text{m}$ . The proposed device showed negligible ambipolar current (10−19 A/ $\mu \text{m}$ ) as negative bias increases to $V_{\mathbf {GS}} =-0.8$ V making the device compatible for low-voltage applications.

Design and Investigation of Charge-Plasma-Based Work Function Engineered Dual-Metal-Heterogeneous Gate Si-Si 0.55 Ge 0.45 GAA-Cylindrical NWTFET for Ambipolar Analysis

Space applications demand highly stable and reliable SRAM circuits for secure and the uninterrupted operation. In this paper, we propose advanced FinFET and self-refreshing logic-based 12T SRAM cell (WWL12T). The dual- ${k}$ gate insulator and symmetric spacer are used to improve the reliability and performance of the FinFET. The outer side high- ${k}$ insulator reduces the charge trapping to the gate oxide and improves the ON current along with reduced short channel effects. WWL12T uses extra word line for bit interleaving aware design and a feedback circuit for stable space applications. In the read operation, the extra ${P}$ -type transistors are active according to the stored data bits and charge the storing nodes using bit-line voltages. The static noise margin and word line write margin of proposed WWL12T SRAM cell under worst case process variation and single charge trapping improve by 6.4% and 8.4%, respectively compared to existing 12T SRAM.

Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design

An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network

Negative bias temperature instability (NBTI) is a major time-dependent reliability concern with the pMOS transistor at elevated temperature. NBTI in pMOS is the severe dominating factor of circuit reliability as it increases the threshold voltage with time. In this paper, an nMOS-only Schmitt trigger with a voltage booster (NST-VB) circuit is proposed. The use of only an nMOS transistor in the critical path of the Schmitt trigger circuit drastically reduces the effect of NBTI on the circuit and, hence, improves performance. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of an nMOS-only structure. Because of NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% compared to 7.2% and 1.47% for the conventional Schmitt trigger and nMOS inverter, respectively, after the stress time of three years. The proposed NST-VB circuit is also validated with an s27 benchmark circuit from the ISCAS’89 benchmark set and found that it has a lower effect of NBTI compared to CMOS and Schmitt trigger inverter circuits. For the viability of the proposed circuit, figure-of-merit (FOM) is used as a performance metric and it is found that the proposed circuit has ${15.11\times }$ improved FOM compared to the conventional Schmitt trigger circuit.

Process Variation and NBTI Resilient Schmitt Trigger for Stable and Reliable Circuits

Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is $189.73\mu W$ which is 63% of the state-of-the-art.

/pdf/recon-resource-efficient-cordic-based-neuron-architecture-ctouwpridy.pdf

RECON: Resource-Efficient CORDIC-Based Neuron Architecture

Negative bias temperature instability (NBTI) is a major reliability issue with the scaled devices at elevated temperature. The effect of NBTI increases with the time, and it increases the threshold voltage of pMOS. In this paper, an on-chip adaptive body bias (O-ABB) circuit to compensate the degradation due to NBTI aging is presented. The O-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin, and word line write margin (WLWM). The O-ABB consists of standby leakage current ( ${I}_{{ddq}}$ ) sensor circuit, decision circuit, and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of ten years NBTI aging. The proposed O-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM, and WLWM decreases by 10.55%, 8.55%, and 3.25%, respectively, in the absence of O-ABB, whereas hold SNM, read SNM, and WLWM decreases by only 0.47%, 1.15%, and 0.62%, respectively, if O-ABB is used to compensate the degradation.

On-Chip Adaptive Body Bias for Reducing the Impact of NBTI on 6T SRAM Cells

A comparative study of cylindrical gate-all-around (Cyl-GAA) tunnel field effect transistor (TFET) based on underlaps with varying spacer width is presented. Extensively, simulation results show that asymmetrical underlap (AU) GAA-TFET with low spacer width enhances the fringing field within the spacer. The proposed device structure has high I ON (6.9 × 10−4 A/µm), low I OFF (2.5 × 10−17 A/µm), and an enhanced I ON/I OFF (1013). This is due to the high series resistance at drain channel junction caused by AU. Furthermore, the proposed structure exhibits a steeper subthreshold swing (30 mV/dec) when compared with symmetrical underlap (SU) Cyl-GAA-TFET.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/mnl.2016.0202

Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width

As an alternative to conventional tunnel field-effect transistor (TFET) devices for low-power applications, drain-underlap (DU) cylindrical (Cyl) gate-all-around (GAA) TFETs based on a Ge source using fringing-field effects can show suppressed subthreshold leakage current. In this work, such a fringing field is implemented using a hetero-spacer dielectric placed over the Ge source, resulting in enhanced direct-current (DC) and analog/radiofrequency (RF) characteristics such as $$I_{\mathrm{ON}}$$
 , $$I_{\mathrm{OFF}}$$
 , subthreshold swing (SS), $$C_{\mathrm{gs}}$$
 , $$C_{\mathrm{gd}}$$
 , and $$f_\mathrm{t}$$
 . It is found that the ambipolar behavior and Miller capacitance $$C_{\mathrm{gd}}$$
 are minimized in combination with a high band-to-band tunneling (BTBT) rate compared with devices based on a homo-spacer dielectric placed over a Si source. At the same time, the drain-underlap design increases the series resistance across the drain–channel junction overlapped by the fringing field, reducing $$I_{\mathrm{OFF}}$$
 . Furthermore, the performance of the proposed device matches well with experimental data when including the effects of trap-assisted tunneling (TAT) for improved device reliability. Thus, the behavior of the RF figure of merit of the proposed device is different compared with conventional TFET designs.

Ankur Beohar

Papers

On-Chip Adaptive Body Bias for Reducing the Impact of NBTI on 6T SRAM Cells

Process Variation and NBTI Resilient Schmitt Trigger for Stable and Reliable Circuits

Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width

Analog/RF characteristics of a 3D-Cyl underlap GAA-TFET based on a Ge source using fringing-field engineering for low-power applications

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells