scispace - formally typeset
A

Antonio J. Lopez-Martin

Researcher at University of Navarra

Publications -  308
Citations -  5019

Antonio J. Lopez-Martin is an academic researcher from University of Navarra. The author has contributed to research in topics: CMOS & Operational amplifier. The author has an hindex of 30, co-authored 301 publications receiving 4513 citations. Previous affiliations of Antonio J. Lopez-Martin include New Mexico State University & Universidad Pública de Navarra.

Papers
More filters
Journal ArticleDOI

Micropower active-RC channel filter for a zero-IF Bluetooth receiver

TL;DR: In this article, a fourth-order low-pass channel filter for a zero-IF Bluetooth receiver is presented, which employs two cascaded multiple feedback biquads and active resistors made by quasi-floating gate MOS transistors in triode region for highly linear continuous tuning.

Radio-Planning, Energy Efficiency, and System Integration

TL;DR: In this article, the impact of radio-planning strategies, transceiver elec- tronic design, and overall wireless system planning is discussed, by following a complete approach, from physical layer limitations derived from radiopropagation losses to transceiver requirements and the functional elements of the overall wireless systems.
Journal ArticleDOI

A Review of Techniques to Enhance an Amplifier’s Performance Using Resistive Local Common Mode Feedback

TL;DR: A review of some of the most common applications of the resistive local common mode feedback technique to enhance amplifier's performance is presented in this paper , where it is shown that this simple technique offers essential improvement in open loop gain, gain-bandwidth product, slew rate, common mode rejection ratio, power supply rejection ratio etc.
Journal ArticleDOI

Low-Voltage Rail-to-Rail Tunable FGMOS Transconductor

TL;DR: In this article, the combined use of a FGMOS differential pair and a floating DC level shifter allows the use of low supply volatages while maintaining at the same time a rail-to-rail input range, low distortion and high linearity.
Proceedings ArticleDOI

An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators

TL;DR: Experimental results obtained from a MOSIS 0.5 mum CMOS technology test chip are shown that validate rail-to-rail operation with a 1.5 V supply voltage.