A
Ardavan Pedram
Researcher at Stanford University
Publications - 37
Citations - 3752
Ardavan Pedram is an academic researcher from Stanford University. The author has contributed to research in topics: Linear algebra & Memory hierarchy. The author has an hindex of 15, co-authored 35 publications receiving 2902 citations. Previous affiliations of Ardavan Pedram include University of Tehran & University of Texas at Austin.
Papers
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Journal ArticleDOI
EIE: efficient inference engine on compressed deep neural network
TL;DR: In this paper, the authors proposed an energy efficient inference engine (EIE) that performs inference on a compressed network model and accelerates the resulting sparse matrix-vector multiplication with weight sharing.
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EIE: Efficient Inference Engine on Compressed Deep Neural Network
TL;DR: An energy efficient inference engine (EIE) that performs inference on this compressed network model and accelerates the resulting sparse matrix-vector multiplication with weight sharing and is 189x and 13x faster when compared to CPU and GPU implementations of the same DNN without compression.
Proceedings ArticleDOI
Plasticine: A Reconfigurable Architecture For Parallel Paterns
Raghu Prabhakar,Yaqi Zhang,David Koeplinger,Matthew Feldman,Tian Zhao,Stefan Hadjis,Ardavan Pedram,Christos Kozyrakis,Kunle Olukotun +8 more
TL;DR: This work designs Plasticine, a new spatially reconfigurable architecture designed to efficiently execute applications composed of parallel patterns that provide an improvement of up to 76.9× in performance-per-Watt over a conventional FPGA over a wide range of dense and sparse applications.
Proceedings ArticleDOI
Spatial: a language and compiler for application accelerators
David Koeplinger,Matthew Feldman,Raghu Prabhakar,Yaqi Zhang,Stefan Hadjis,Ruben Fiszel,Tian Zhao,Luigi Nardi,Ardavan Pedram,Christos Kozyrakis,Kunle Olukotun +10 more
TL;DR: This work describes a new domain-specific language and compiler called Spatial for higher level descriptions of application accelerators, and summarizes the compiler passes required to support these abstractions, including pipeline scheduling, automatic memory banking, and automated design tuning driven by active machine learning.
Journal ArticleDOI
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era
TL;DR: The dark memory state and present Pareto curves for compute units, accelerators, and on-chip memory, and motivates the need for HW/SW codesign for parallelism and locality are discussed.