R
Raghu Prabhakar
Researcher at Stanford University
Publications - 25
Citations - 671
Raghu Prabhakar is an academic researcher from Stanford University. The author has contributed to research in topics: Plasticine & Reconfigurable computing. The author has an hindex of 9, co-authored 21 publications receiving 465 citations. Previous affiliations of Raghu Prabhakar include University of California, Los Angeles & University of California.
Papers
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Proceedings ArticleDOI
Plasticine: A Reconfigurable Architecture For Parallel Paterns
Raghu Prabhakar,Yaqi Zhang,David Koeplinger,Matthew Feldman,Tian Zhao,Stefan Hadjis,Ardavan Pedram,Christos Kozyrakis,Kunle Olukotun +8 more
TL;DR: This work designs Plasticine, a new spatially reconfigurable architecture designed to efficiently execute applications composed of parallel patterns that provide an improvement of up to 76.9× in performance-per-Watt over a conventional FPGA over a wide range of dense and sparse applications.
Proceedings ArticleDOI
Spatial: a language and compiler for application accelerators
David Koeplinger,Matthew Feldman,Raghu Prabhakar,Yaqi Zhang,Stefan Hadjis,Ruben Fiszel,Tian Zhao,Luigi Nardi,Ardavan Pedram,Christos Kozyrakis,Kunle Olukotun +10 more
TL;DR: This work describes a new domain-specific language and compiler called Spatial for higher level descriptions of application accelerators, and summarizes the compiler passes required to support these abstractions, including pipeline scheduling, automatic memory banking, and automated design tuning driven by active machine learning.
Journal ArticleDOI
Automatic generation of efficient accelerators for reconfigurable hardware
David Koeplinger,Christina Delimitrou,Raghu Prabhakar,Christos Kozyrakis,Yaqi Zhang,Kunle Olukotun +5 more
TL;DR: A hybrid area estimation technique which uses template-level models and design-level artificial neural networks to account for effects from hardware place-and-route tools, including routing overheads, register and block RAM duplication, and LUT packing is described.
Proceedings ArticleDOI
Generating Configurable Hardware from Parallel Patterns
Raghu Prabhakar,David Koeplinger,Kevin J. Brown,HyoukJoong Lee,Christopher De Sa,Christos Kozyrakis,Kunle Olukotun +6 more
TL;DR: This paper presents a general representation of tiled parallel patterns, and provides rules for automatically tiling patterns and generating metapipelines, and demonstrates experimentally that these optimizations result in speedups up to 39.4× on a set of benchmarks from the data analytics domain.
Proceedings ArticleDOI
Static and dynamic co-optimizations for blocks mapping in hybrid caches
TL;DR: A combined static and dynamic scheme is proposed to optimize the block placement for endurance and energy-efficiency in a hybrid SRAM and STT-RAM cache that uses the compiler to provide static hints to guide initial data placement, and the hardware to correct the hints based on the run-time cache behavior.