Showing papers in "IEEE Design & Test of Computers in 2017"
TL;DR: The authors have provided a classification in CPS Domains, Attacks, Defenses, Research-trends, Network-security, Security level implementation, and Computational Strategies which makes this survey a unique and I believe very helpful article.
Abstract: The following is a survey on surveys and may help the interested reader to find a way through the jungle of literature on the security and CPS topics out there already In order to ease the search, the authors have provided a classification in CPS Domains, Attacks, Defenses, Research-trends, Network-security, Security level implementation, and Computational Strategies which makes this survey a unique and I believe very helpful article —Jorg Henkel, Karlsruhe Institute of Technology
253 citations
TL;DR: An important attempt is made in the form of the AxBench suite, which contains applications for CPUs, GPUs, and hardware design with necessary annotations to mark the approximable regions and output quality metrics.
Abstract: Approximate computing is claimed to be a powerful knob for alleviating the peak power and energy-efficiency issues. However, providing a consistent benchmark suit with diverse applications amenable to approximate computing is crucial to ensure fair and reproducible comparisons. This article makes an important attempt toward it in the form of the AxBench suite, which contains applications for CPUs, GPUs, and hardware design with necessary annotations to mark the approximable regions and output quality metrics. —Muhammad Shafique, Vienna University of Technology
186 citations
TL;DR: The dark memory state and present Pareto curves for compute units, accelerators, and on-chip memory, and motivates the need for HW/SW codesign for parallelism and locality are discussed.
Abstract: Unlike traditional dark silicon works that attack the computing logic, this article puts a focus on the memory part, which dissipates most of the energy for memory-bound CPU applications. This article discusses the dark memory state and present Pareto curves for compute units, accelerators, and on-chip memory, and motivates the need for HW/SW codesign for parallelism and locality. –Muhammad Shafique, Vienna University of Technology
121 citations
TL;DR: The authors summarize the state-of-the-art probing and anti-probing technologies and their challenges, and discuss the opportunities in the relevant research.
Abstract: Editor’s note: As a type of invasive physical attacks, probing attacks are able to access and directly monitor security critical nets of an IC and extract sensitive information. In this paper, the authors summarize the state-of-the-art probing and anti-probing technologies and their challenges, and discuss the opportunities in the relevant research. —Yiran Chen, Duke University
76 citations
TL;DR: This paper provides a tutorial overview of the state-of-the-art in verification of complex and heterogeneous Systems-on-Chip.
Abstract: Editor’s note: This paper provides a tutorial overview of the state-of-the-art in verification of complex and heterogeneous Systems-on-Chip. The authors discuss current industrial trends and key research challenges. —Haralampos Stratigopoulos, Sorbonne Universites, UPMC, CNRS, LIP6
61 citations
TL;DR: This article provides a comprehensive high-level overview of the various facets of post-silicon validation, and includes industrial case studies illustrating their real-life application.
Abstract: Editor’s note: Post-silicon validation is a complex and critical component of a modern system-on-chip (SoC) design verification. It includes a large number of inter-related activities each with its own nuance and subtleties, requires extensive planning, and spans the entire system design lifecycle. This article provides a comprehensive high-level overview of the various facets of post-silicon validation, and includes industrial case studies illustrating their real-life application. — Swarup Bhunia, University of Florida
53 citations
TL;DR: This tutorial gives a structured insight into the field of design space exploration for embedded systems and finds the best compromise between different design goals and their tradeoff.
Abstract: Editor's note :As embedded systems grow more complex and as new applications such as IoT require many design constraints, sophisticated design space exploration techniques are essential in order to find the best compromise between different design goals and their tradeoff. This tutorial gives a structured insight into the field of design space exploration for embedded systems.
53 citations
TL;DR: A comprehensive survey of reliability enhancement techniques for three mainstream emerging memories and a summary of the possible future research directions in this area are offered.
Abstract: Editor’s note: Reliability continues to be a severe challenge in the development of emerging memories. In this article, the authors offer a comprehensive survey of reliability enhancement techniques for three mainstream emerging memories and a summary of the possible future research directions in this area. —Yiran Chen, Duke University
42 citations
TL;DR: This paper presents an overview centered around the paradigm of self-awareness in computing systems, which helps systems to understand, manage, and report on their own system behavior.
Abstract: Editor’s note: Self-awareness is a desirable feature of emerging computing systems. It helps systems to understand, manage, and report on their own system behavior. This paper presents an overview centered around the paradigm of self-awareness in computing systems. —Partha Pratim Pande, Washington State University
41 citations
TL;DR: A very low power encoder design is proposed using a sparse, hyperdimensional representation of letters and words in natural language and it is shown that this representation and their design can be used with high energy efficiency for a language recognition task.
Abstract: Editor’s note: Online learning for data analysis, categorization and anomaly detection has become a key technique in a range of adaptive embedded applications. In this article the authors propose a very low power encoder design using a sparse, hyperdimensional representation of letters and words in natural language and they show that this representation and their design can be used with high energy efficiency for a language recognition task. — Axel Jantsch, Royal Institute of Technology Electronics, Computer and Software Systems
39 citations
TL;DR: As an introduction to the Special Issue on Dark Silicon, the authors provide the newest trends and a survey on the topic that has valuable information for novices and experts alike.
Abstract: Power density has become the major constraint for many on-chip designs. As an introduction to the Special Issue on Dark Silicon, the authors provide the newest trends and a survey on the topic that has valuable information for novices and experts alike.
TL;DR: This article investigates how to leverage analog emissions (vibration, acoustic, magnetic, and power) of 3D printers in order to identify the printed object and compromise confidentiality.
Abstract: As 3-D printers are becoming increasingly relevant in various domains, including critical infrastructure, cyber-security questions naturally arise. This article investigates how to leverage analog emissions (vibration, acoustic, magnetic, and power) of 3-D printers in order to identify the printed object and compromise confidentiality. — Michail Maniatakos, New York University Abu Dhabi
TL;DR: The authors explore the intrinsic trade-off in a DRAM between the power consumption (due to refresh) and the reliability and their unique platform allows tailoring to the design constraints depending on whether power consumption, performance or reliability has the highest design priority.
Abstract: Editor’s note: The authors explore the intrinsic trade-off in a DRAM between the power consumption (due to refresh) and the reliability. Their unique platform allows tailoring to the design constraints depending on whether power consumption, performance or reliability has the highest design priority. —Jorg Henkel, Karlsruhe Institute of Technology
TL;DR: This article presents a testbed for water infrastructures capable of accurately assessing the effectiveness of cybersecurity solutions that are economically infeasible and lacks flexibility.
Abstract: Testing cybersecurity techniques for critical infrastructure on real-world setups is economically infeasible and lacks flexibility. In order to address this challenge, this article presents a testbed for water infrastructures capable of accurately assessing the effectiveness of cybersecurity solutions. –Michail Maniatakos, New York University Abu Dhabi
TL;DR: This new system can help operators of the power grid detect when device settings have been tampered, and help identified the context of a command.
Abstract: This article focuses on detecting attacks to power system with the help of cyber-physical co-modeling. The foundational algorithm used to detect attacks is a new dynamic state estimator that can provide real-tie models of the system improving over legacy state estimators and three-phase linear state estimators. This new system can help operators of the power grid detect when device settings have been tampered, and help identified the context of a command (i.e., under which conditions of the system are specific commands allowed). —Alvaro Cardenas, University of Texas at Dallas
TL;DR: Challenges and opportunities for designing complex system on chips that can operate in the near-threshold voltage range are discussed and evaluation for 32 and 22-nm test chips is presented.
Abstract: Near-threshold computing has emerged as an attractive paradigm for energy efficiency. This article discusses challenges and opportunities for designing complex system on chips that can operate in the near-threshold voltage range. Evaluation for 32- and 22-nm test chips is presented.
TL;DR: The authors summarize the latest research progress of phase change memory, spin-transfer torque random access memory, and resistiverandom access memory in device engineering, circuit design, computer architecture, and application.
Abstract: Editor’s note: Phase change memory, spin-transfer torque random access memory, and resistive random access memory are three major emerging memory technologies that receive tremendous attentions from both academia and industry. In this survey article, the authors summarize the latest research progress of these technologies in device engineering, circuit design, computer architecture, and application. —Tei-Wei Kuo, National Taiwan University
Journal Article•
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TL;DR: This special issue on “Dark Silicon” presents various ways to make the best use of all on-chip cores even though power density is at a limit and implied that a large amount of cores would need to be idle (stay “dark”) in order to cope with the power density.
Abstract: Power density is one of the most stringent constraints in designing on-chip systems. This seems surprising at first sight considering that the switching energy of a transistor in current CMOS technology is only about a 1/1000 of what it used to be a quarter century ago. Still, power density is rapidly increasing. One of the main causes is that voltage can hardly be scaled further down (see also “Dennard Scaling”). As a result, not all the core of many multicore chips can run simultaneously at the highest performance level. Cooling is either too expensive or simply impossible. This observation led to the notion of “Dark Silicon.” It was initially coined in a paper from the computer architecture community (“Dark silicon and the end of multicore scaling,” ISCA 2011) and later on, it was adapted by the design automation community with various special session and invited talks on major conferences which sparked new ideas. It implied that a large amount of cores would need to be idle (stay “dark”) in order to cope with the power density. It is clear though that the silicon footprint is too expensive to let cores idle. This special issue on “Dark Silicon” takes this challenge and presents various ways to make the best use of all on-chip cores even though power density is at a limit. Many thanks to the Guest Editors Muhammad Shafique, Siddharth Garg, and Vikas Chandra, who brought this interesting topic to the IEEE Design&Test with five papers plus a comprehensive survey on the topic.
TL;DR: TSV-based 3-D stacking enables large-capacity, power-efficient DRAMs with high bandwidth, such as specified by JEDEC's HBM standard, to be tested at SK hynix.
Abstract: TSV-based 3-D stacking enables large-capacity, power-efficient DRAMs with high bandwidth, such as specified by JEDEC's HBM standard. This article is a written version of Jun's very interesting presentation at 3D-TEST 2015 on how such DRAM stacks are tested at SK hynix.
TL;DR: An overview of 3-D integration along with various design challenges and recent innovations is presented, to achieve "More Moore and More Than Moore".
Abstract: Three-dimensional (3-D) integration, a breakthrough technology to achieve “More Moore and More Than Moore,” provides numerous benefits, e.g., higher performance, lower power consumption, and higher bandwidth, by utilizing vertical interconnects and die/wafer stacking. This paper presents an overview of 3-D integration along with various design challenges and recent innovations. — Partha Pande, Washington State University
TL;DR: This survey summarizes the state-of-art for trusted hardware design in AMS/RF IC’s, and highlights directions towards advancing the field.
Abstract: Editor’s note: The trustworthiness of integrated circuits is now an essential technical and business challenge for the semiconductor industry. In the digital domain, there has been extensive activity in understanding and counteracting the threats of hardware Trojans, piracy and counterfeiting. However, this research area is largely nascent and understudied for analog/mixed-signal (AMS) and radio frequency (RF) circuits, which are widely used in contemporary systems. This survey summarizes the state-of-art for trusted hardware design in AMS/RF IC’s, and highlights directions towards advancing the field. – Steven Nowick, Columbia University
TL;DR: This issue of IEEE Design&Test is on merging memories and is accompanied by a comprehensive survey “Recent Technology Advances of Emerging Memories” focusing primarily on phase change memory, spin-transfer torque random access memory, and resistiverandom access memory.
Abstract: The focus of this issue of IEEE Design&Test (D&T) is on merging memories and is brought to us by Yiran Chen, Tei-Wei Kuo, and Barbara de Salvo. Emerging memory technologies have significant advantages in some of the typical memory characteristics but fall short in others such that their broad adoption continues to be a challenge. This special issue highlights the most prominent problems and their current solutions. The special issue is accompanied by a comprehensive survey “Recent Technology Advances of Emerging Memories” focusing primarily on phase change memory, spin-transfer torque random access memory, and resistive random access memory, which serves as an introduction to the topic.
TL;DR: This article proposes a new transmission-gate approach to filter out soft errors, and it is more efficient when to the thanks to its to compared state of art solutions, capability adjust gate and body bias voltages.
Abstract: Soft errors not only are major threats to SRAM, but also have become a major threat to the reliability of logic circuits. This article proposes a new transmission-gate approach to filter out soft errors, and it is more efficient when to the thanks to its to compared state of art solutions, capability adjust gate and body bias voltages.
TL;DR: This paper proposes to make higher levels aware of variations of process parameters, operational voltage, and temperature (PVT variations) and bring them under system control by using software controlled body biasing.
Abstract: Editor’s note: As technology edges closer to fundamental limits, variations of process parameters, operational voltage, and temperature (PVT variations) have to be accounted for. This paper proposes to make higher levels aware of these variations and bring them under system control by using software controlled body biasing. PVT variations can thus be exploited to reduce power and energy consumption.— Axel Jantsch, TU Wien
TL;DR: The article shows designers how they can sometimes take advantage of these interdependencies to safely reduce design margins, while in other cases, it is possible that the interdependency conspire to amplify the effect of the degradation effects in catastrophic ways.
Abstract: Editor’s note: Process variations, aging and wearout, are nonidealities that lead to suboptimal system performance and increased power. In order to understand the effects of these degradation effects, until now, researchers have investigated them thoroughly, but separately from each other. What this article shows is that process variations and wearout are not independent from each other and they need to be considered together. The article shows designers how they can sometimes take advantage of these interdependencies to safely reduce design margins, while in other cases, it is possible that the interdependencies conspire to amplify the effect of the degradation effects in catastrophic ways. —Mircea Stan, University of Virginia
TL;DR: This paper, based on an excellent keynote address by AMD's Jeff Rearick at 3D-TEST 2015, describes the design and test development of one of the world's first high-volume 3D die stacks and hence a landmark product: AMD's Fury GPU.
Abstract: This paper, based on an excellent keynote address by AMD's Jeff Rearick at 3D-TEST 2015, describes the design and test development of one of the world's first high-volume 3-D die stacks and hence a landmark product: AMD's Fury GPU.
TL;DR: This article presents an approach to extend mathematical formal analysis towards verification of linear analog circuits with real-time applications.
Abstract: Editor’s note: This article presents an approach to extend mathematical formal analysis towards verification of linear analog circuits. — Jayanta Bhadra, NXP
TL;DR: A complete fault management solution that includes fault detection and categorization, maintaining a map of faults, and modified scheduling and application algorithms for using healthy resources only is presented.
Abstract: Editor’s note: Motivated by the need to tolerate faults, this paper presents a complete fault management solution that includes fault detection and categorization, maintaining a map of faults, and modified scheduling and application algorithms for using healthy resources only. As the system maintains fairly sophisticated models of itself regarding faulty and healthy resources, it constitutes a good example of specialized self-awareness. —Axel Jantsch, TU Wien
TL;DR: The authors present some design techniques of nonvolatile processors with a multisource energy-harvesting system that combines thermal, kinetic, and indoor photovoltaic sources to provide a stable power supply.
Abstract: Editor’s note: One promising application of emerging memories is to implement a nonvolatile memory hierarchy that can retain the data when power is removed. In this work, the authors present some design techniques of nonvolatile processors with a multisource energy-harvesting system that combines thermal, kinetic, and indoor photovoltaic sources to provide a stable power supply. —Yiran Chen, Duke University
TL;DR: The ongoing Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR) is described, and the different candidates of the competition with respect to a variety of metrics of relevance to constrained systems, including their memory footprints are compared.
Abstract: In this article, the authors study the problem of efficient authenticated encryption algorithms for use in embedded devices. In particular, they describe the ongoing Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR), and compare the different candidates of the competition with respect to a variety of metrics of relevance to constrained systems, including their memory footprints. —Alvaro Cardenas, University of Texas at Dallas