Showing papers by "Aris Christou published in 1995"
TL;DR: In this article, a model for calculating the currentvoltage characteristics of strained In/sub 0.52/Al/Sub 0.48/As/In/sub x/Ga/sub 1-x/As on InP substrate High Electron Mobility Transistors (HEMT's), based on a variational charge control model, is presented.
Abstract: A model for the calculation of the current-voltage characteristics of strained In/sub 0.52/Al/sub 0.48/As/In/sub x/Ga/sub 1-x/As on InP substrate High Electron Mobility Transistors (HEMT's), based on a variational charge control model, is presented. A polynomial fit of the two-dimensional electron gas (2DEG) density is used for the calculation of the current-voltage characteristics. The effect of strain is introduced into the 2DEG density versus gate voltage relation. Very good agreement between the calculated and measured I-V characteristics was obtained. In addition, our results show that, for an indium mole fraction of the In/sub x/Ga/sub 1-x/As channel in the range 0.53-0.60, increasing the indium mole fraction lowers the threshold voltage and hence increases the drain current at the same gate bias. >
15 citations
TL;DR: In this article, a diffusion controlled degradation model based on a modified Whipple-type grain boundary diffusion model has been developed for closed-packed array (Bi,Sb) 2 (Te,Se) 3 compound semiconductor power thermoelectric modules caused by the formation of dark bands.
Abstract: Closed-packed array (Bi,Sb) 2 (Te,Se) 3 compound semiconductor thermoelectric power modules have been used extensively in terrestrial thermoelectric generators for converting thermal energy directly into electricity. In this paper a diffusion controlled degradation model based on a new modified Whipple-type grain boundary diffusion model has been developed. This model considers the effect of temperature gradient on a high diffusivity path and has been developed for studying the degradation mechanism of (Bi,Sb) 2 (Te,Se) 3 compound semiconductor power thermoelectric modules caused by the formation of dark bands.
5 citations
TL;DR: In this article, the effects of power and temperature cycling on crack propagation at the die attach were investigated and it was found that stresses developed on the die because of the environmental temperature changes and their dissipation as part of an effective thermal management is necessary to ensure reliable performance.
Abstract: Stresses induced at the GaAs-Al2O3 interface by large ΔT excursions have been investigated by finite element simulation and have been correlated with experimental results. The effects of power and temperature cycling on crack propagation at the die attach are investigated. The FEA (finite element analysis) method is used to simulate the effect of die attach voids on the peak surface temperature and on the die stresses. These voids in the die attach are identified to be the major cause of die cracking. It was found that stresses developed on the die because of the environmental temperature changes and their dissipation as part of an effective thermal management is necessary to ensure reliable performance.
4 citations
TL;DR: In this paper, an application of the physics-of-failure design philosophy to flip-chip bonds in a microelectronic package is presented, which uses knowledge of the life-cycle load profile, package architecture and material properties to identify potential failure mechanisms and to prevent operational failures through robust design and manufacturing practices.
Abstract: This paper presents an application of the physics‐of‐failure design philosophy to flip‐chip bonds in a microelectronic package. The physics‐of‐failure philosophy utilises knowledge of the life‐cycle load profile, package architecture and material properties to identify potential failure mechanisms and to prevent operational failures through robust design and manufacturing practices. The potential failure mechanisms and failure sites are identified in this paper for flip‐chip bonds, and an approach is presented to prevent the identified potential failure mechanisms by design. Finally, quality conformance issues are discussed to ensure a robust manufacturing process and qualification issues are addressed to evaluate the reliability of the designed flip‐chip bond.
2 citations
TL;DR: In this paper, a numerical investigation has been conducted in order to demonstrate the potential thermal performance that can be achieved by utilizing a diamond heat sink design which minimizes junction-to-case thermal resistance.
Abstract: A numerical investigation has been conducted in order to demonstrate the potential thermal performance that can be achieved by utilizing a diamond heat - sink design which minimizes junction - to - case thermal resistance. Effects of the thermal conductivity of the substrate material, the thermal conductivity of the die attach material, the substrate thickness, and the die attach thickness on the thermal resistance are addressed. The results indicate that the temperature increase could be 3 to 4 times less with diamond heat-sinks when compared to other materials.
1 citations
TL;DR: In this paper, the authors investigated the electrical properties of n-GaAs epilayers grown by MBE on the top of L.T.GaAs and found that the Hall mobility and the channel depth of the epilayer decreases as the growth temperature of the buffer decreases.
Abstract: We have investigated the electrical properties of n-GaAs epilayers grown by MBE on the top of L.T.GaAs .The Hall mobility and the channel depth of the epilayer decreases as the growth temperature of the buffer decreases. The degradation of the electrical properties is attributed to the outdiffusion of precipitates and point defects from the L.T. buffer layer. The use of intermediate layers (GaAs grown at 400°C-600°C and GaAs/AlxGa1-xAs (x=0.5, 1) superlattices ) between L.T. buffer and n-GaAs active layers in MESFET devices improves the Hall mobility of the channel, the gm and fT performance of the devices.This improvement has been attributed to the AlGaAs layer which hinders the defects outdiffusion.