Satellite communications methods include receiving communications signals including co-channel interference at a space-based component from a plurality of wireless terminals in a satellite footprint over a satellite frequency band and reducing interference in the communication signals by (a) performing co-channel interference reduction on the communications signals to generate a plurality of interference reduced signals and (b) performing multiple access interference cancellation on the interference reduced signals. An interference reducing detector for a satellite communications system includes an interference reducer configured to perform co-channel interference reduction on communications signals to generate a plurality of interference reduced signals, and a detector configured to perform multiple access interference cancellation on the interference reduced signals. Satellite communications systems and satellite gateways including interference reducing detectors are also disclosed.

Adaptive beam forming with multi-user detection and interference reduction in satellite communication systems and methods

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

Method for novel SOI DRAM BICMOS NPN

A sense amplifier apparatus for use in a memory array having a plurality of memory cells is provided. The sense amplifier apparatus includes a differential sense amplifier and a dynamic sense amplifier. The differential sense amplifier has a first set of switches for driving the voltages of the sense amplifier apparatus and are coupled to a complementary pair of outputs. Also provided are a second set of switches, which are coupled to a complementary pair of input lines so as to amplify the input signal on either of the pair of input lines to a first signal level at a first rate of amplification. The dynamic sense amplifier shares the first set of switches with the differential sense amplifier and further includes a third set of switches that are coupled to a complementary pair of input lines and the output lines and also a sense enable line. This allows the first signal level to be amplified to a second signal level at a second rate of amplification faster than the first rate of amplification.

Two mode sense amplifier with latch

An 8Kb domino read SRAM with hit logic and parity checker, fabricated in a 65nm SOI CMOS technology (Leobandung, 2005), is described. A key feature is the elimination of the traditional sense amplifier to reduce timing and design complexity. The focus of this paper is to demonstrate a memory array, comprised of 6T cells, that can generate near "rail-to-rail" bit-line voltage differentials that can be driven off macro without the aid of sense amplifiers. Therefore, short, low capacitance bit-line segments (or sub-arrays) are cascaded together to form larger bit-line structures, achieving performance and density goals with robust operation over a wide range of process and environmental conditions.

A 8Kb domino read SRAM with hit logic and parity checker

A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently.

Local bit select with suppression of fast read before write

A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

Global bit line restore timing scheme and circuit

Statistical approaches for yield estimation and robust design are vital in the current variation-dominated design era. This article presents a mixture importance sampling methodology to enable yield-driven design and extends its application beyond memories to peripheral circuits and logic blocks.

The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane

A latch and driver circuit is disclosed for use in reading out data from a random access memory cell. The invention, which may be implemented in BICMOS technology, accomplishes high-speed asynchronous latching, level translation and output driving operations. The invention includes a latch and at least one output driver coupled in parallel to a latch driver.

Arthur D. Tuminaro

Papers

A 8Kb domino read SRAM with hit logic and parity checker

Local bit select with suppression of fast read before write

Global bit line restore timing scheme and circuit

The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane

Latch and data out driver for memory arrays