Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding has become a key element in device processing over the past years. Today, although solutions for wafer support systems have made great progress in terms of process performance, thin wafer debonding and handling remains extremely challenging. Our motivation to move away from thermoplastic high temperature melt debonding materials to room temperature debondable materials is clearly exposed in this paper: we describe the process integration and manufacturing aspects of the Brewer Science® ZoneBOND® temporary bonding process, as a one-to-one alternative to the Brewer Science® WaferBOND® HT-10.10 slide debonding material. Process issues related to the material integration into complex 3D flows as well as key learnings are described in details. One important modification that was required is related to the edge-trimming process that is typically performed on the active device wafer prior to bonding and grinding. The ZoneBOND® material was found not to be compatible with this process, resulting in permanent defects and damages during grinding. To resolve this issue, the process flow was modified to an edge-trimming after wafer bonding approach. Finally, the room temperature debonding process is fully described.

Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications

Electromigration failure locations in three-dimensional (3D) interconnect structures with high-aspect-ratio through silicon vias, (TSVs, Φ5 × 50 µm2) connected to 40-µm-pitch CuSn solder joints have been identified using test structures which were designed to avoid failures in the back-end-of-line (BEOL). The resistance of the structures with the TSV and bump connections showed a continuous increase until failure. For the structures without a bump connection, where only TSV and re-distributed line (RDL) were the electrically connected, the resistance remained constant prior to the final failure. From cross-sectional analyses after the test, the failure locations were identified at the TSV bottom or at the bump bottom. The location of void formation was changed by applied current direction. The flux divergence generated by the barrier metal and the reservoir effect plays a crucial role in the void formation, and each failure mode is considered to have a different impact on the reliability performance.

https://iopscience.iop.org/article/10.7567/JJAP.54.05EE01/pdf

Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices

We report the development of a bi-layer spin on temporary bonding solution (TBS) which eliminates the need for specialized equipment for wafer pretreatment to enable bonding or wafer post treatment for debonding. Thus it greatly increases the throughput of the temporary bonding/debonding process. It also provides a total thickness variation (TTV) of less than 1 μm for spin coated films on both 200 mm and 300 mm wafers which enable the TTV of 300 mm bonded pairs to be 2-3 μm for bumped wafers using 70 and 100 μm thick adhesive films after backgrinding for an unoptimized bonding process. Furthermore, we have demonstrated the chemical and thermal stability of both the material and the bonded pair by exposing the bonded wafer pair to common chemicals (phosphoric acid, nitric acid, organic solvents etc.) and temperature conditions (up to 300 C) used in the TSV process. Additionally, the time taken for the entire spin coat-bond-debond process was less than 15 minutes with room for further improvement. Based on the current results, it is expected that the current bi-layer based temporary bonding solution has the potential to play an important role in enabling the high volume manufacturing of 2.5D/3D IC stacking.

/pdf/low-cost-room-temperature-debondable-spin-on-temporary-24c62yoi3p.pdf

Low cost, room temperature debondable spin-on temporary bonding solution: A key enabler for 2.5D/3D IC packaging

Over the past few years, temporary bonding has spread together with the development of 3D stacked IC (SIC) technology. Maturity of the various processes has constantly improved. Early processes enabled first demonstration of circuit thinning and thin wafer debonding. Each material generation has brought a step function in the technology maturity, which is now reaching a level allowing first 3D-SIC production. To further answer the refraining elements preventing a more massive technology adoption, novel temporary bonding materials and processes are being developed to reach even lower stress and wafer breakage risks. Hence this contribution deals with the early demonstration of a novel laser release process for ultralow-force debonding.

Extremely Low-Force Debonding of Thinned CMOS Substrate by Laser Release of a Temporary Bonding Material

Thin-wafer handling is one of the key enabling technologies for 2.5D/3D IC integration. Usually, it temporary bonds the TSV (through-silicon via)/RDL (redistribution layer) wafer (e.g., passive and active interposers) to a supporting carrier wafer with an adhesive, backgrinds the TSV/RDL interposer wafer to very thin (≤100μm), goes through all the necessary processes, and then de-bonds the thin TSV/RDL interposer wafer from the carrier wafer. In this study, a different route will be taken which eliminates the temporary bonding and de-bonding processes. Emphasis is placed on using a heat-spreader wafer as a supporting carrier wafer during the manufacturing processes and after the assembly is completed (diced), the heat-spreader remains on the thin TSV/RDL interposer. This is a very simple and low-cost thin-wafer handling method for 2.5D/3D IC integration.

Thin-Wafer Handling with a Heat-Spreader Wafer for 2.5D/3D IC Integration

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on a novel ZoneBOND approach to face these challenges.

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on extensive characterization of a thermal debonding approach to answer these challenges.

Process characterization of thin wafer debonding with thermoplastic materials

Among the technological developments pushed by the emergence of 3D-ICs, wafer thinning has become a key element in device processing over the past years. As volume increases, defects in the overall thinning process flow will become a major element of focus in the future. Indeed product wafers arriving at this point of process are of maximum value. Fundamental understanding of the potential defects and their impact on devices is therefore needed to minimize their recurrence.

Axel Van den Eede

Papers

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Process characterization of thin wafer debonding with thermoplastic materials

Temporary wafer bonding defect impact assessment on substrate thinning: Process enhancement through systematic defect track down