Samuel Suhard

TL;DR: In this paper, gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7A EOT, ∼2x higher f max performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence.

TL;DR: In this article, the junctionless gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral configuration were compared to the conventional gate-and-allow mode (IM) GAA-NPNs, showing similar speed and voltage gain, and reduced LF noise.

TL;DR: This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency.

TL;DR: In this paper, a bumpless process is introduced in order to further scale down the pitch of microbumps, and electrical resistance measurement, cross section SEM and mechanical characterizations show successful 3D stacking using proposed method.