Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction-diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.

A Comparative Study of Different Physics-Based NBTI Models

A comprehensive modeling framework is presented to predict the time kinetics of negative bias temperature instability stress and recovery during and after dc and ac stresses and also during mixed dc–ac stress. The model uses uncorrelated contributions from the generation of interface and bulk traps and hole trapping in preexisting bulk traps. Ultrafast measured data at different stresses and recovery biases, temperature, duty cycle and frequency, as well as arbitrary time segments with dynamically varying voltage, frequency, and activity are predicted. The role of nitrogen in the gate insulator is explained. End-of-life degradation is determined under dc and ac use conditions.

BTI Analysis Tool—Modeling of NBTI DC, AC Stress and Recovery Time Kinetics, Nitrogen Impact, and EOL Estimation

Hardware security and trust have become a pressing issue during the last two decades due to the globalization of the semiconductor supply chain and ubiquitous network connection of computing devices. Computing hardware is now an attractive attack surface for launching powerful cross-layer security attacks, allowing attackers to infer secret information, hijack control flow, compromise system root-of-trust, steal intellectual property (IP), and fool machine learners. On the other hand, security practitioners have been making tremendous efforts in developing protection techniques and design tools to detect hardware vulnerabilities and fortify hardware design against various known hardware attacks. This article presents an overview of hardware security and trust from the perspectives of threats, countermeasures, and design tools. By introducing the most recent advances in hardware security research and developments, we aim to motivate hardware designers and electronic design automation tool developers to consider the new challenges and opportunities of incorporating an additional dimension of security into robust hardware design, testing, and verification.

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An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Threshold voltage shift ( $\Delta {\text V}_{\text T}$ ) due to negative-bias temperature instability (NBTI) in p-FinFETs with replacement metal gate-based high-k metal gate process is measured using an ultrafast method. A comprehensive modeling framework involving uncorrelated contributions from the generation of interface traps ( $\Delta {\text V}_{\text {IT}}$ ), hole trapping in preexisting ( $\Delta {\text V}_{\text {HT}}$ ), and generation of new ( $\Delta {\text V}_{\text {OT}}$ ) bulk insulator traps is used to quantify measured data. The model can explain dc stress and recovery data over an extended temperature range (−40 °C to 150 °C), for different stress and recovery biases. It can explain ac stress and recovery data for different bias, temperature, frequency, and duty cycle. The differences in time kinetics and temperature activation of $\Delta {\text V}_{\text {IT}}$ , $\Delta {\text V}_{\text {HT}}$ , and $\Delta {\text V}_{\text {OT}}$ , and their relative dominance at various experimental conditions are shown. End-of-life NBTI for dc and ac stress is estimated by using the model and compared to prediction from conventional analytical methods.

Ultrafast Measurements and Physical Modeling of NBTI Stress and Recovery in RMG FinFETs Under Diverse DC–AC Experimental Conditions

Controversial issues in negative bias temperature instability

A comprehensive NBTI framework using the H/H2 RD model for interface traps and 2 well model for hole traps has been proposed and used to predict DC and AC experiments. The framework is validated against experimental data from different DC stress and recovery conditions, AC frequency and duty cycle, measurement speed, and across SiON and HKMG devices having different gate insulator processes. Limitations of the alternative 2 stage model framework is discussed.

B. Jose

Papers

A Comparative Study of Different Physics-Based NBTI Models

A comprehensive AC / DC NBTI model: Stress, recovery, frequency, duty cycle and process dependence