Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

It has been over a decade since neural networks were first applied to solve combinatorial optimization problems. During this period, enthusiasm has been erratic as new approaches are developed and (sometimes years later) their limitations are realized. This article briefly summarizes the work that has been done and presents the current standing of neural networks for combinatorial optimization by considering each of the major classes of combinatorial optimization problems. Areas which have not yet been studied are identified for future research.

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Neural Networks for Combinatorial Optimization: a Review of More Than a Decade of Research

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8-/spl mu/m CMOS process with V/sub tn/=0.72 V and V/sub tp/=-0.75 V. For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51/spl deg/ phase margin, 0.33-V//spl mu/s slew rate, 3.54-/spl mu/s settling time, and 426-/spl mu/W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption.

Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

First, new stability conditions for low-power CMOS nested Miller compensated amplifiers are given in this brief. Then, an improved structure, which takes the advantages of a feedforward transconductance stage and a nulling resistor, is introduced. Experimental results prove that the proposed structure improves the frequency response, transient response, and power supply rejection ratio without increasing the power consumption and circuit complexity.

Nested Miller compensation in low-power CMOS design

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-mum CMOS process. Experimental results show a greatly improved slew rate by factors 30-60 and gain-bandwidth product by factors 11.5-17 when compared to a classical Class-A OTA. The circuits are operated at plusmn1-V supply voltage with only 10 muA of bias current

Super Class-AB OTAs With Adaptive Biasing and Dynamic Output Current Scaling

The architecture associated with the Hopfield network can be utilized in the VLSI realization of several important engineering optimization functions for signal processing purposes. The properties of local minima in the energy function of Hopfield networks are investigated. A design technique to eliminate these local minima in the Hopfield neural-based analog-to-digital converter has been developed. Experimental data agree well with theoretical results in the output characteristics of the neural-based data converter. >

Design of a neural-based A/D converter using modified Hopfield network

A prototype very-large-scale integrated circuit (VLSI) reliability simulator is described. Software modules for hot-carrier effects have been developed. Popular substrate current models are implemented in the simulator. Experiments were performed to establish the relationship between transistor model parameter changes and the substrate current level. The circuit reliability simulation techniques can be extended to include dielectric breakdown and interconnect electromigration effects. >

An integrated-circuit reliability simulator-RELY

The performances of several types of analog VLSI circuits are limited by the setting behavior of CMOS amplifiers. An amplifier with a nonsaturated input stage which achieves a high slew-rate response is presented. The impact of this slew-rate amplifier on switched-capacitor circuits is described. Prototyping amplifier circuits were fabricated by the MOSIS service using a 2- mu m scalable CMOS technology. When biased at a DC power dissipation of 1 mW, the two-stage amplifier achieves a slew rate of 80 V/ mu s, a positive-supply rejection ratio of 73 dB, and a negative-supply rejection ratio of 57 dB and 50 kHz. >

A high slew-rate CMOS amplifier for analog signal processing

Circuit cells for DRAM-style programmable synapses and gain-adjustable neurons, which achieve high packing density and hardware annealing, are described. The 8-b accuracy in synapse weights can be achieved in a 0.2-s refresh cycle and the gain-adjustable neurons can be used to apply the hardware annealing technique for efficient searching of the optimal solution. >

B.W. Lee

Papers

Design of a neural-based A/D converter using modified Hopfield network

An integrated-circuit reliability simulator-RELY

A high slew-rate CMOS amplifier for analog signal processing

General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons