Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

2.4. Block Copolymer Containing Hybrids 151 3. Block Copolymer Ordering in Thin Films 153 3.1. General Process Steps 153 3.2. Morphology of Thin Films 154 3.3. Thickness-Dependent Nanopatterning 154 3.3.1. Ultrathin Films: Monomolecular Films 155 3.3.2. Sub-L0 Thick Films 155 3.3.3. Thick Films 157 3.4. Placement Control: Directed Self-Assembly (DSA) 162 3.4.1. Topographic Guiding Patterns: Graphoepitaxy 163

Block copolymer based nanostructures: materials, processes, and applications to electronics.

Recent research and development has been incredibly successful at advancing the capabilities for vacuum electronic device (VED) sources of powerful terahertz (THz) and near-THz coherent radiation, both CW or average and pulsed. Currently, the VED source portfolio covers over 12 orders of magnitude in power (mW-to-GW) and two orders of magnitude in frequency (from ; 10 THz). Further advances are still possible and anticipated. They will be enabled by improved understanding of fundamental beam-wave interactions, electromagnetic mode competition and mode control, along with research and development of new materials, fabrication methods, cathodes, electron beam alignment and focusing, magnet technologies, THz metrology and advanced, broadband output radiation coupling techniques.

Vacuum Electronic High Power Terahertz Sources

This self-contained, comprehensive book describes the fundamental properties of soft x-rays and extreme ultraviolet (EUV) radiation and discusses their applications in a wide variety of fields, including EUV lithography for semiconductor chip manufacture and soft x-ray biomicroscopy. The author begins by presenting the relevant basic principles such as radiation and scattering, wave propagation, diffraction, and coherence. He then goes on to examine a broad range of phenomena and applications. The topics covered include EUV lithography, biomicroscopy, spectromicroscopy, EUV astronomy, synchrotron radiation, and soft x-ray lasers. He also provides a great deal of useful reference material such as electron binding energies, characteristic emission lines and photo-absorption cross-sections. The book will be of great interest to graduate students and researchers in engineering, physics, chemistry, and the life sciences. It will also appeal to practicing engineers involved in semiconductor fabrication and materials science.

X-Rays and Extreme Ultraviolet Radiation: Principles and Applications

We report direct observation of an unexpected anisotropic swelling of Si nanowires during lithiation against either a solid electrolyte with a lithium counter-electrode or a liquid electrolyte with a LiCoO2 counter-electrode. Such anisotropic expansion is attributed to the interfacial processes of accommodating large volumetric strains at the lithiation reaction front that depend sensitively on the crystallographic orientation. This anisotropic swelling results in lithiated Si nanowires with a remarkable dumbbell-shaped cross section, which develops due to plastic flow and an ensuing necking instability that is induced by the tensile hoop stress buildup in the lithiated shell. The plasticity-driven morphological instabilities often lead to fracture in lithiated nanowires, now captured in video. These results provide important insight into the battery degradation mechanisms.

Anisotropic Swelling and Fracture of Silicon Nanowires during Lithiation

High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily with microelectromechanical systems. In recent years, through-silicon-via (TSV) etch applications for three-dimensional integrated circuit stacking technology has spurred research and development of this enabling technology. This potential large scale application requires HAR etch with high and stable throughput, controllable profile and surface properties, and low costs.

High aspect ratio silicon etch: A review

Extreme ultraviolet lithography (EUVL) was thoroughly reviewed over a broad range of topics, including history, tools, source, metrology, condenser and projection optics, resists, and masks. Since 1988, many studies on EUVL have been conducted in North America, Europe, and Japan, through state sponsored programs and industrial consortiums. To date, no “show stopper” has been identified, but challenges are present in almost all aspects of EUVL technology. Commercial alpha lithography step-and-scan tools are installed with full-field capability; however, EUVL power at intermediate focus (IF) has not yet met volume manufacturing requirements. Compared with the target of 180W IF power, current tools can supply only approximately 55–62W. EUV IF power has been improved gradually from xenon- to tin-discharge-produced plasma or laser-produced plasma. EUVL resist has improved significantly in the last few years, with 25nm 1:1 line/space resolution being produced with approximately 2.7nm (3σ) line edge roughness. A...

Extreme ultraviolet lithography: A review

The present invention provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a microwave power generator coupled to the to the chamber body through a waveguild, and one or more coils or magnets disposed around an outer circumference of the chamber body adjacent to the waveguide, and a gas source coupled to the waveguide through a gas delivery passageway.

Methods and apparatus for controlling photoresist line width roughness

Extreme ultraviolet lithography (EUVL) and three dimensional integrated circuit (3D IC) were thoroughly reviewed. Since proposed in 1988, EUVL obtained intensive studies globally and, after 2000, became the most promising next generation lithography method even though challenges were present in almost all aspects of EUVL technology. Commercial step-and-scan tools for preproduction are installed now with full field capability; however, EUV source power at intermediate focus (IF) has not yet met volume manufacturing requirements. Compared with the target of 200 W in-band power at IF, current tools can supply only approximately 40–55 W. EUVL resist has improved significantly in the last few years, with 13 nm line/space half-pitch resolution being produced with approximately 3–4 nm line width roughness (LWR), but LWR needs 2× improvement. Creating a defect-free EUVL mask is currently an obstacle. Actual adoption of EUVL for 22 nm and beyond technology nodes will depend on the extension of current optical lithography (193 nm immersion lithography, combined with multiple patterning techniques), as well as other methods such as 3D IC. Lithography has been the enabler for IC performance improvement by increasing device density, clock rate, and transistor rate. However, after the turn of the century, IC scaling resulted in short-channel effect, which decreases power efficiency dramatically, so clock frequency almost stopped increasing. Although further IC scaling by lithography reduces gate delay, interconnect delay and memory wall are dominant in determining the IC performance. 3D IC technology is a critical technology today because it offers a reasonable route to further improve IC performance. It increases device density, reduces the interconnect delay, and breaks memory wall with the application of 3D stacking using through silicon via. 3D IC also makes one chip package have more functional diversification than those enhanced only by shrinking the size of the features. The main advantages of 3D IC are the smaller form factor, low energy consumption, high speed, and functional diversification. EUVL, if adopted, will continue to enable IC performance improvement at a slower rate, but 3D IC provides an alternative way to improve the system performance. The best scenario is the adoption of both EUVL and 3D IC. However, the possible further delay of EUVL could enhance the realization of 3D IC for IC system improvement.

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

The present invention provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.

Banqiu Wu

Papers

High aspect ratio silicon etch: A review

Extreme ultraviolet lithography: A review

Methods and apparatus for controlling photoresist line width roughness

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

Methods and apparatus for controlling photoresist line width roughness with enhanced electron spin control