Showing papers by "Baoxing Duan published in 2021"

Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

Abstract: A novel Si/SiC heterojunction Lateral Double-diffused Metal Oxide Semiconductor with the Semi-Insulating Polycrystalline Silicon field plate (SIPOS Si/SiC LDMOS) is proposed in this paper for the first time. The innovative terminal technology of Breakdown Point Transfer (BPT) had been applied on Si/SiC MOSFETs. This creative technology improved Breakdown Voltage (BV) of the proposed device, compared with the conventional Si LDMOS (Cov. LDMOS). In order to optimize the trade-off between BV and Specific On-Resistance ( $\text{R}_{\mathrm{ ON,SP}}$ ), the SIPOS field plate is applied on Si/SiC LDMOS for the first time in this paper. At On-State, due to the internal electric field of SIPOS filed plate, the majority carriers accumulation layer is formed on the surface of the drift region for the proposed SIPOS Si/SiC LDMOS, which means $\text{R}_{ON,SP}$ will be reduced. Meanwhile, the electric field modulation effect of SIPOS field plate can make the surface electric field distribute evenly, which leads to an increase of BV. In addition, due to the high-thermal conductivity of SiC substrate, the heat-dissipation efficiency of the proposed device is significantly improved. The simulation results show that the BV of SIPOS Si/SiC LDMOS is 428.4V, which increased by 78.4% in comparison with Cov. LDMOS ( BV of 240.0V) with the same structure parameters. The $\text{R}_{\mathrm{ ON,SP}}$ of SIPOS Si/SiC LDMOS is decreased from $33.2{\mathrm{ m}}\Omega \cdot {\mathrm{ cm}}^{2}$ of Cov. LDMOS to $24.0{\mathrm{ m}}\Omega \cdot {\mathrm{ cm}}^{2}$ , decreased by 27.7%. Furthermore, the figure-of-merit (FOM = BV2/ $\text{R}_{\mathrm{ on,sp}}$ ) of SIPOS Si/SiC LDMOS reaches 7.6MW/cm2, which means SIPOS Si/SiC LDMOS has enough performance to break the Silicon limit.

Experimental Results for AlGaN/GaN HEMTs Improving Breakdown Voltage and Output Current by Electric Field Modulation

Abstract: A depletion-mode AlGaN/GaN high electron mobility transistors (HEMTs) have been proposed in this article with the partial GaN cap, which applies the electric field modulation effect to optimize the surface electric field and two-dimensional electron gas (2DEG) distribution. The 2DEG density under the partial GaN cap is reduced due to the polarization effect formed by the partial GaN cap and AlGaN layers. The surface electric field is reshaped by the electric field modulation effect due to the partial GaN cap, featuring an extra electric field peak far away from the gate edge, which, therefore, improves the breakdown voltage (BV). Moreover, the output current ( ${I}_{\text {DS}}$ ) is also improved slightly resulting from the increased mobility of 2DEG, which compensates for the decrease in the 2DEG density. The experimental BV is increased greatly from 378 V for the conventional AlGaN/GaN HEMTs to 656 V for the depletion-mode partial cap layer AlGaN/GaN HEMTs because of the optimized surface electric field by the electric field modulation effect. The maximum output current ( ${I}_{\text {max}}$ ) is increased from 538 to 558 mA/mm. It is concluded that the BV can be improved significantly and ${I}_{\text {DS}}$ increased slightly for AlGaN/GaN HEMTs by the electric field modulation technique using the partial GaN cap, which optimizes the BV and specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}, \text {sp}}$ ) simultaneously.

Accumulation-Mode Lateral Double-Diffused MOSFET Breaking Silicon Limit by Eliminating Dependence of Specific ON-Resistance on Doping Concentration

Abstract: An accumulation-mode lateral double-diffused MOSFET (LDMOS) is proposed and its mechanism is investigated in this article. To optimize the tradeoff between breakdown voltage (BV) and specific ON-resistance ( ${R}_{\text {on,sp}}$ ), the idea of separating the breakdown area from the conduction path is designed. The N-type buffer layer is adopted to obtain ideal reverse characteristics for accumulation-mode LDMOS. The electrons are introduced to eliminate the dependence of the ${R}_{\text {on,sp}}$ on the doping concentration of the drift region. Simulation results show that the ${R}_{\text {on,sp}}$ of the proposed LDMOS is 6.83 $\text{m}\Omega \cdot \text {cm}^{{2}}$ with the BV of 460 V, which is less than 30.2 $\text{m}\Omega \cdot \text {cm}^{{2}}$ that of the conventional LDMOS with the BV of 223 V for the same drift region length of $20~\mu \text{m}$ . Moreover, the ${R}_{\text {on,sp}}$ of ac-NBL LDMOS is only 2.07 $\text{m}\Omega \cdot \text {cm}^{{2}}$ , which is reduced by 93% compared with the conventional LDMOS with the same BV of 223 V. A better tradeoff between BV and ${R}_{\text {on,sp}}$ can be obtained by eliminating the dependence of ${R}_{\text {on,sp}}$ on the doping concentration, and the ${R}_{\text {on},\text {sp}}$ of ac-NBL LDMOS increases much more slowly than that of conventional LDMOS as BV increases.

Experimental of Folded Accumulation Lateral Double-diffused Transistor with Low Specific On Resistance

Abstract: In power devices, the resistance of the drift region becomes a dominant portion of the total device. In order to reduce the on resistance, the folded accumulation lateral double-diffused MOSFET (FALDMOS) is proposed and manufactured. The drift region of FALDMOS is etched to form the folded surface, which is similar to the FinFET structure. The drift region is surrounded by the extended gate. The electric field of the drift region can be modulated by the extended gate in three-dimensional when the device is turned off. Therefore, the concentration of the drift region can be greatly increased. When the device is turned on, a large amount of electrons can be introduced in the sidewall of the drift region to increase the conductivity, thereby obtaining ultra-low on resistance. The FALDMOS is manufactured by 0.35μm BCD technology and the experimental results show that the specific on resistance of FALDMOS is only 9.3 mΩ•mm2, while that of the conventional LDMOS is 36.2mΩ•mm2, which is reduced by 74.3% with the same breakdown voltage of 36V. In addition, the current density of FALDMOS is 5 times higher than the conventional LDMOS in the same area.

Novel SOI LDMOS Without RESURF Effect by Flexible Substrate for Flexible Electronic Systems

Abstract: In this article, laterally diffused MOS (LDMOS) combined with flexible substrate polydimethylsiloxane (PDMS) which can be used in flexible electronic system is described. The flexible substrate has insulation characteristics, which makes the original substrate float; thus, the substrate electrode and reduce surface electric field (RESURF) technology are missing. The simulation results show that the breakdown voltage (BV) of LDMOS combined with PDMS decreases by 23.3%. Considering that most flexible electronic systems require thin functional layers to achieve portability, the use of SOI LDMOS can achieve better performance on thinner substrates. Then, through simulation, the flexible substrate will reduce the BV of the SOI LDMOS by 17.4%, and combined with experiments and tests, it is verified that the flexible substrate will indeed reduce the BV of the SOI LDMOS by 15%, which is basically consistent with the simulation results. But there is no obvious effect on the specific ON-resistance ( ${R} _{ \mathrm{ON},\text {sp}}$ ). For the phenomenon of substrate floating, a new structure named surface electrodes trench drift region SOI LDMOS (SETD SOI LDMOS) is proposed. After optimizing the simulation, compared with conventional SOI LDMOS, the SOI LDMOS combined with the flexible substrate can achieve a 57.54% increase in the BV while reducing ${R} _{ \mathrm{ON},\text {sp}}$ by 11%.

Novel Vertical Power MOSFET With Step Hk Insulator Close to Super Junction Limit Relationship Between Breakdown Voltage and Specific ON-Resistance by Improving Electric Field Modulation

Abstract: A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- ${k}$ (Hk) MOSFET concept in this article with the step high- ${k}$ insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of $42~\mu \text{m}$ . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

Novel fast-switching LIGBT with P-buried layer and partial SOI

Abstract: A novel silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed in this paper. The proposed device has a P-type buried layer and a partial-SOI layer, which is called the BPSOI-LIGBT. Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer, the proposed structure generates two new peaks in the surface electric field distribution, which can achieve a smaller device size with a higher breakdown voltage. The smaller size of the device is beneficial to the fast switching. The simulation shows that under the same size, the breakdown voltage of the BPSOI LIGBT is 26% higher than that of the conventional partial-SOI LIGBT (PSOI LIGBT), and 84% higher than the traditional SOI LIGBT. When the forward voltage drop is 2.05 V, the turn-off time of the BPSOI LIGBT is 71% shorter than that of the traditional SOI LIGBT. Therefore, the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT. In addition, the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.

New Strained Silicon-On-Insulator Lateral MOSFET With Ultralow ON-Resistance by Si 1-x Ge x P-Top Layer and Trench Gate

Abstract: A novel ultralow on-resistance strained silicon-on-insulator (SOI) lateral double-diffused MOSFET with silicon-germanium (Si1-xGex) P-top layer and trench gate (PSiGe-TG LDMOS) is proposed in this letter. The Si1-xGex P-top layer (PSiGe) as a stressor introduces the beneficial stress in the drift and channel regions to enhance the electron mobility. Besides, in the off state, both P-top layer and trench gate (TG) jointly assist in depleting the N-drift region, which leads to an allowable highly-doped N-drift region. As a consequence, PSiGe-TG LDMOS realizes an ultralow specific on-resistance ( ${R}_{\text {on,sp}}$ ) resulting from the highly-doped N-drift region. Furthermore, the enhanced electric field in the trench oxide leads to an increase in breakdown voltage ( BV ). The simulation results show that, compared with the trench-gate SOI LDMOS (TG LDMOS) and the trench-gate SOI LDMOS with Si-based P-top layer (PSi-TG LDMOS), the introduction of PSiGe layer leads to 42% and 26% reduction in ${R}_{\text {on,sp}}$ , respectively. The figure-of-merit ( FOM ) of PSiGe-TG LDMOS increases from 8.1 MW/cm2 of TG LDMOS and 9.4 MW/cm2 of PSi-TG LDMOS to 12 MW/cm2, which realizes a superior performance.