Showing papers by "Bernabe Linares-Barranco published in 1992"

Generation, design and tuning of OTA-C high frequency sinusoidal oscillators

Abstract: A systematic approach to derive practical CMOS sinusoidal oscillators is presented. A general topology is given to implement sinusoidal oscillators by using operational transconductance amplifier capacitor (OTA-C) techniques. To illustrate the proposed approach five different structures are presented from this general topology and analysed, taking into account the CMOS OTAs dominant non-idealities. Building blocks are presented for amplitude control, both by automatic gain control (AGC) schemes and by limitation schemes. Experimental results from 3 μm and 2 μm CMOS (MOSIS) prototypes showing oscillation frequencies up to 69 MHz are included. The amplitudes can be adjusted between 1 V peak-to-peak and 100 mV peak-to-peak. Total harmonic distortions (THD) from 2.8% down to 0.2% have been experimentally measured in the laboratory. A frequency tuning loop for these structures is introduced that provides a precise, temperature and parasitic independent frequency-to-voltage relationship. Experimental results for the tuning loop are presented.

A modular T-mode design approach for analog neural network hardware implementations

Abstract: A modular transconductance-mode (T-mode) design approach is presented for analog hardware implementations of neural networks. This design approach is used to build a modular bidirectional associative memory network. The authors show that the size of the whole system can be increased by interconnecting more modular chips. It is also shown that by changing the interconnection strategy different neural network systems can be implemented, such as a Hopfield network, a winner-take-all network, a simplified ART 1 network, or a constrained optimization network. Experimentally measured results from CMOS 2- mu m double-metal, double-polysilicon prototypes (MOSIS) are presented. >

CMOS analog neural network systems based on oscillatory neurons

Abstract: The authors discuss the design of two neural network systems based on the use of pulsing neurons Each neuron was built as a simple voltage controlled oscillator (VCO) whose control voltage made the circuit oscillate or not oscillate The interconnecting synapses between neurons are made with programmable transconductance amplifiers The weight of each synapse is represented by the transconductance gain of the amplifiers, and is externally adjustable for each synapse The oscillatory neuron circuit and the interconnection strategy for oscillatory neurons are described Using this technique a 5-neuron Hopfield network and 6-neuron bidirectional associated memory (BAM) network were built and tested, using standard 2- mu m double-metal, double polysilicon CMOS (MOSIS) chips >

Modular analog continuous-time VLSI neural networks with on-chip Hebbian learning and analog storage

Abstract: A modular analog circuit design approach for hardware implementations of neural networks is presented. This approach is based on the use of small transconductance multipliers as the main component, and is therefore called the T-mode (transconductance-mode) approach. This circuit design technique was used to design a set of modular chips which assembled to build either BAM (bidirectional associative memory) networks, Hopfield networks, winner-take-all networks, or simplified ART1 networks. The approach is extended afterwards in order to include a Hebbian learning rule into each synapse. As an example, a learning BAM network system is shown. The experimental results given were obtained from 2- mu m CMOS double-metal double-polysilicon (MOSIS) prototypes. >

Modular T-mode neural network learning hardware implementations with analog storage capability

Abstract: A modular T-mode (transconductance-mode) design approach is presented for analog hardware implementations of neural networks. This design approach is used to build a BAM network, a Hopfield network, a winner-take-all network, and a simplified ART1 network. The size of these networks can be increased by interconnecting more modular chips together. The approach is extended to include synaptic Hebbian learning as well as an analog scheme to refresh the learned weights. Experimental results of programmable and learning chips from a standard 2- mu m double-metal double-poly CMOS process (MOSIS) are given. >