This paper presents an in-depth analysis of the effectiveness of on-chip and package decoupling capacitors in light of the interaction between chip-package resonance and the frequency content of switching sources, and suggests an approach for decoupling analysis in fast turn-around ASIC designs, achieving both simulation efficiency and accuracy. The analysis is based on accurate modeling of the on-chip and package power supply structures of ASIC flip-chip modules as distributed networks to provide precise understanding of switching noise mechanisms in distributed power supply structures in both the time and frequency domains. The simulation efficiency versus accuracy of two types of package models is discussed. The local effectiveness of on-chip and package decoupling capacitors is illustrated using detailed, frequency-domain impedance profiles of the on-chip and package power supply networks, demonstrating location-dependant responses that vary according to the local placement of decoupling capacitors. Based on the study, a methodology is presented for accurately determining the quantities and locations of on-chip decoupling capacitors required to limit on-chip transient power supply collapse to a pre-defined level.

The effects of on-chip and package decoupling capacitors and an efficient ASIC decoupling methodology

The multichip module (MCM) that contains the central electronic complex (CEC) of the S/390 G5 system is described in this paper. The glass-ceramic module, topped with six layers of polyimide full-field thin-film wiring for chipto-chip interconnection, represents IBM’s most advanced packaging technology. This MCM provides a large wiring capacity, with 595 meters of routed interconnection; it supports the highest synchronous interconnection performance in the industry at 300 MHz; and it allows for cooling flexibility at the system level—either a heat sink for air-cooled systems or a cooling “hat” for systems using refrigeration cooling. The physical and electrical characteristics of this packaging technology, necessary to support the aggressive system performance goals (1040 MIPS) of the IBM G5 Enterprise Servers, are presented here. In addition, the approach used to produce a robust electrical and physical design is described.

MCM technology and design for the S/390 G5 system

Glasses are materials that lack a crystalline microstructure and long-range atomic order. Instead, they feature heterogeneity and disorder on superstructural scales, which have profound consequences for their elastic response, material strength, fracture toughness, and the characteristics of dynamic fracture. These structure-property relations present a rich field of study in fundamental glass physics and are also becoming increasingly important in the design of modern materials with improved mechanical performance. A first step in this direction involves glass-like materials that retain optical transparency and the haptics of classical glass products, while overcoming the limitations of brittleness. Among these, novel types of oxide glasses, hybrid glasses, phase-separated glasses, and bioinspired glass-polymer composites hold significant promise. Such materials are designed from the bottom-up, building on structure-property relations, modeling of stresses and strains at relevant length scales, and machine learning predictions. Their fabrication requires a more scientifically driven approach to materials design and processing, building on the physics of structural disorder and its consequences for structural rearrangements, defect initiation, and dynamic fracture in response to mechanical load. In this article, a perspective is provided on this highly interdisciplinary field of research in terms of its most recent challenges and opportunities. 

/pdf/advancing-the-mechanical-performance-of-glasses-perspectives-2z3c7eec.pdf

Advancing the Mechanical Performance of Glasses: Perspectives and Challenges

Glass substrates are emerging as a key alternative to silicon and conventional organic substrates for high-density and high-performance systems due to their outstanding dimensional stability, enabling sub-5- $\mu \text{m}$ lithographic design rules, excellent electrical performance, and unique mechanical properties, key in achieving board-level reliability at body sizes larger than $15\times15$ mm2. This paper describes the first demonstration of the board-level reliability of such large, ultrathin glass ball grid array (BGA) packages directly mounted onto a system board, considering both their thermal cycling and drop-test performances. To investigate board-level reliability, glass BGA packages, $18.5\times18.5$ mm2 in body size and 100 $\mu \text{m}$ in thickness, were first designed and fabricated with a daisy-chain pattern. The glass test vehicles were fabricated at panel level, and then BGA balled by ball drop process with SAC105 solder balls, 250 $\mu \text{m}$ in diameter at 400- $\mu \text{m}$ pitch. After singulation, the glass packages were mounted onto printed circuit boards using standard surface mount technology assembly processes, and then subjected to reliability testing through thermal cycling and drop tests following JEDEC reliability standards. The effect of the coefficient of thermal expansion (CTE) of glass was evaluated by investigating low- and high-CTE glass substrates, with the CTEs of 3.8 and 9.8 ppm/°C, respectively. While all glass packages passed 1000 thermal cycles at −40/125 °C as predicted by thermomechanical modeling using the Engelmaier–Wild model, the fatigue life of high-CTE samples exceeded 5000 thermal cycles. In addition, 28/30 drop-test samples passed the required 40 and 200 drops on corner and inner circuits, respectively, with no clear effect of the glass CTE. The predominant failure modes were systematically identified for both reliability tests.

Board-Level Thermal Cycling and Drop-Test Reliability of Large, Ultrathin Glass BGA Packages for Smart Mobile Applications

This article deals with the reliability of a power semiconductor exposing to the severe thermal stresses. The importance of solder joint thickness on the power semiconductor's useful lifetime is demonstrated in this article. Solder layer thickness has knock on effects both on the creep accumulated strain and thermal characteristics of the power semiconductors. Since, these effects are in contradictory of each other, a trade-off seems to be essential to optimize the solder layer thickness. Thereby, thermo-mechanical behavior of a discrete power semiconductor under the thermal mission profile was simulated and the results were integrated to the actual conditions. The simulation results reveal that after thermal cycling, some creep strain is produced in the solder layer especially at the corners. The thinner the solder joint was, the greater accumulated creep strain was observed leading to the faster degradation. On the contrary, the thicker the solder layer was, the larger thermal resistance was observed leading to the higher junction temperature. Accordingly, the article is concentrated on optimizing the solder layer thickness based on these two issues. The scanning electron microscope micrographs, the EDS maps and X-ray diffraction analysis were also taken to indicate the solder layer thickness effects on the number of voids and their propagations in the different solder layer thicknesses. The experimental tests validate the expected results in the extracted simulations.

Reliability Enhancement of a Power Semiconductor With Optimized Solder Layer Thickness

This paper reports the first demonstration of the drop-test reliability performance of large, ultra-thin glass BGA packages that are directly mounted onto the system board, unlike the current approach of flip-chip assembly of interposers, involving additional organic packages which are then SMT assembled onto boards. The packages, 18.4mm × 18.4mm in size made of 100µm-thick glass, were also successfully assembled, for the first time, in a SMT line. The effect on drop reliability of the glass BGAs with circumferential polymer collars was studied extensively. While the glass BGA packages met the reliability requirements, both with and without polymer collars, the polymer collars were found to further enhance the drop performance, as well as the fatigue life of solders. Finite element modeling was used to understand strain-relief mechanisms and provide design guidelines for reliability. The glass substrates fabrication process along with the formation of polymer collars by spin coating is detailed. The glass package-to-PCB assemblies were formed using SMT-compatible processes with standard equipment, followed by reliability testing through thermal cycling and drop tests. The compiled failure data from drop testing was fitted into a Weibull distribution plot. Comprehensive failure analysis was performed to assess the structural integrity of the glass substrates and identify the predominant failure mechanisms in drop test.

First demonstration of drop-test reliability of ultra-thin glass BGA packages directly assembled on boards for smartphone applications

For the first time, compact physical models are derived in this work that enable quick package- and chip-scale calculations of the power supply noise and incorporate the distributed natures of on-chip power/ground grids and package-level power/ground planes. Designers can use these models to perform chip/package co-design for power distribution networks and tradeoff multiple design considerations such as metal resource allocation on chip and in package, decoupling capacitor insertion and I/O allocation. Such studies can be performed during early stages of design, even when detailed physical design information is not available. The models are used to model a ceramic package designed by IBM, and it is found that there is less than 10% difference between the model predictions and the commercial tool SPEED 2000 when predicting the peak noise value and time of occurrence. The models can have 10times speed-up compared to SPEED 2000.

Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI)

In this paper the effect of on-chip thin oxide decoupling capacitors on power supply noise due to internal logic switching will be presented. The effect of logic switching on power supply noise as function of, amount of capacitance, capacitance placement, voltage, temperature and frequency of operation will be characterized. Results of both measurements and simulations will be presented.

http://ieeexplore.ieee.org/iel4/5582/14953/00678757.pdf

Core logic simultaneous switching noise measurements on a 500 MHz CMOS chip on a CBGA SCM

The needs for higher speed and bandwidth at low power for portable and high-performance applications has been driving recent innovations in packaging technologies with new substrate platforms with finer lithographic capability and dimensional stability, such as ultra-thin glass, to enable off-chip interconnections pitch scaling, down to 30µm. Copper pillar flip-chip thermocompression bonding (TCB) has subsequently become a pervasive technology in the past decade, and is now considered as the next interconnection and assembly node for smart mobile and high-performance systems. However, additional innovations are needed to achieve high-throughput thermocompression bonding on fragile and thin glass, with short cycle times and process conditions within HVM (high-volume manufacturing) tool capability. These include material advances in surface finishes and pre-applied underfill materials with built-in flux, along with a unique co-development strategy to provide high-speed solutions with optimized TCB profiles that consider the dynamic thermal behavior of high-density glass substrates, underfill curing kinetics, as well as tool compatibility. These innovations are the key focus of this paper. Finite element heat transfer and thermomechanical modeling were carried out to emulate assembly processes and compare the behavior of glass substrates to that of current technologies. Residual stresses created during the cool-down phase were extracted to help define process windows for stress management in interconnections, by fine control of intermetallics (IMC) formation. Emerging surface finish chemistries compatible with high-density wiring with sub-10µm spacings, such as OSP or EPAG (electroless Pd, autocatalytic Au) finish, were also evaluated for their effect on the formed IMC systems. A new set of no-flow snap-cure underfill materials with high thermal stability, beyond existing conductive films or pastes, was developed in synergy with tools and processes for compatibility with advanced substrate technologies. Model predictions were validated with assembly trials on ultra-thin glass and organic substrates with 100µm thin cores. Design guidelines for bonding tools, materials and processes were finally derived, for high-speed thermocompression bonding, customized to the performance, reliability and cost needs of next-generation mobile and high-performance systems.

Bhupender Singh

Papers

Board-Level Thermal Cycling and Drop-Test Reliability of Large, Ultrathin Glass BGA Packages for Smart Mobile Applications

First demonstration of drop-test reliability of ultra-thin glass BGA packages directly assembled on boards for smartphone applications

Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI)

Core logic simultaneous switching noise measurements on a 500 MHz CMOS chip on a CBGA SCM

Interconnection materials, processes and tools for fine-pitch panel assembly of ultra-thin glass substrates