A method for providing unequal allocation of rights among agents while operating according to fair principles, comprising assigning a hierarchal rank to each agent; providing a synthetic economic value to a first set of agents at the a high level of the hierarchy; allocating portions of the synthetic economic value by the first set of agents to a second set of agents at respectively different hierarchal rank than the first set of agents; and conducting an auction amongst agents using the synthetic economic value as the currency. A method for allocation among agents, comprising assigning a wealth generation function for generating future wealth to each of a plurality of agents, communicating subjective market information between agents, and transferring wealth generated by the secure wealth generation function between agents in consideration of a market transaction. The method may further comprise the step of transferring at least a portion of the wealth generation function between agents.

Multifactorial optimization system and method

A system and method for communicating in a communication network, comprising presenting a communication comprising data over a communications network to a router, said router being adapted to route the communication to one of a plurality of available network destinations; automatically executing a communication targeting algorithm in the router, based at least in part on the data, wherein the communication targeting algorithm operates to contextually jointly analyze a plurality of parameters extracted from the data and a plurality of contextual parameters, to determine an optimum target for the communication, wherein the optimum target varies in dependence on both the data and the context of the communication; and routing the communication in dependence on the algorithm execution.

Telephony control system with intelligent call routing

This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (<0.6° rms error) across a ±50° steering range without requiring calibration. A maximum saturated effective isotropic radiated power of 54 dBm is measured in the broadside direction for each polarization. Tapering control without requiring calibration achieves up to 20-dB sidelobe rejection without affecting the main lobe direction.

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications

This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel ( $2\times 2$ ) transmit/receive (TRX) quad-core chips in SiGe BiCMOS with flip-chip packaging. Each channel of the quad-core beamformer chip has 4.6-dB noise figure (NF) in the receive (RX) mode and 10.5-dBm output 1-dB compression point (OP1dB) in the transmit (TX) mode with 6-bit phase control and 14-dB gain control. The phase change with gain control is only ±3°, allowing orthogonality between the variable gain amplifier and the phase shifter. The chip has high RX linearity (IP1dB = −22 dBm/channel) and consumes 130 mW in the RX mode and 200 mW in the TX mode at P1dB per channel. Advantages of the scalable all-RF beamforming architecture and circuit design techniques are discussed in detail. 4- and 32-element phased-arrays are demonstrated with detailed data link measurements using a single or eight of the four-channel TRX core chips on a low-cost printed circuit board with microstrip antennas. The 32-element array achieves an effective isotropic radiated power (EIRP) of 43 dBm at P1dB, a 45-dBm saturated EIRP, and a record-level system NF of 5.2 dB when the beamformer loss and transceiver NF are taken into account and can scan to ±50° in azimuth and ±25° in elevation with < −12-dB sidelobes and without any phase or amplitude calibration. A wireless link is demonstrated using two 32-element phased-arrays with a state-of-the-art data rate of 1.0–1.6 Gb/s in a single beam using 16-QAM waveforms over all scan angles at a link distance of 300 m.

A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a $2\times 2$ Beamformer Flip-Chip Unit Cell

A 64-channel massive multiple-input multiple-output (MIMO) transceiver with a fully digital beamforming (DBF) architecture for fifth-generation millimeter-wave communications is presented in this paper. The DBF-based massive MIMO transceiver is operated at 28-GHz band with a 500-MHz signal bandwidth and the time division duplex mode. The antenna elements are arranged as a 2-D array, which has 16 columns (horizontal direction) and 4 rows (vertical direction) for a better beamforming resolution in the horizontal plane. To achieve half-wavelength element spacing in the horizontal direction, a new sectorial transceiver array design with a bent substrate-integrated waveguide is proposed. The measured results show that an excellent RF performance is achieved. The system performance is tested with the over-the-air technique to verify the feasibility of the proposed DBF-based massive MIMO transceiver for high data rate millimeter-wave communications. Using the beam-tracking technique and two streams of QAM-64 signals, the proposed millimeter-wave MIMO transceiver can achieve a steady 5.3-Gb/s throughput for a single user in fast mobile environments. In the multiple-user MIMO scenario, by delivering 20 noncoherent data streams to eight four-channel user terminals, it achieves a downlink peak data rate of 50.73 Gb/s with the spectral efficiency of 101.5 b/s/Hz.

Digital Beamforming-Based Massive MIMO Transceiver for 5G Millimeter-Wave Communications

Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high data-rates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1–3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-polarized operation in both RX and TX remains unaddressed, and high output power comes at the cost of power consumption, cooling complexity and increased size. The RFIC reported here addresses these challenges. It supports concurrent and independent dual-polarized operation in TX and RX modes, and is compatible with a volume-efficient, scaled, antenna-in-package array. A new TX/RX switch at the shared antenna interface enables high output power without sacrificing TX efficiency, and a t-line-based phase shifter achieves <1° RMS error and <5° phase steps for precise beam control.

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication

A ringtrip detector comprises a reference counter for controlling a battery current generator, which shapes the ring signal, a zero pass detector for detecting zero passes in a voltage at a node, which is proportional to the telephone line current and two other counters. The zero passes of the voltage create a pulse at both the positive and the negative zero crossing of the zero pass detector. The reference counter is gated into a memory, when these pulses appear. The zero passing of the previous and the present ring cycle are stored in the memory. A counter decides the difference between the previous and the present ring cycles zero passes. If the zero pass difference between the present and previous ring cycles is greater than a fixed value, the output will indicate a 'phase difference' and if it is less than the fixed value it will indicate 'no phase difference'. Another counter counts a predetermined number of successive ring cycles with 'no phase difference' at the start of a ring burst signal, and after establishing the ring burst signal, another predetermined number of successive ring cycles with 'phase difference' is counted to detect the ringtrip.

Bo Bokinge

Papers

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication

Method and device for detecting a ringtrip