Mark Ferriss

TL;DR: This paper presents the first reported 28-GHz phased-array IC for 5G communications, implemented in 130-nm SiGe BiCMOS, which includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation.

TL;DR: In this paper, a continuous-rate clock and data recovery (CDR) circuit that operates from 12.5 Mb/s to 2.7 Gb/s is described, which automatically detects a change in input data rate, acquires the new frequency, and reports the data rate to the user without the need for an external reference clock or any programming.

TL;DR: A prototype 25 GHz VCO based on transconductance linearization of the active devices is integrated in a dual-path PLL and achieves superior performance compared to the state of the art.

TL;DR: In this paper, a multi-function, dual-polarization phased array transceiver supporting both radar and communication applications at W-band is presented, which includes two independent 16:1 combining networks, two receiver downconversion chains, an up-conversion chain, a 40GHz PLL, an 80GHz frequency doubler, extensive digital control circuitry, and on-chip IF/LO combining/distribution circuitry to enable scalability to arrays at the board level.

TL;DR: In this work an all-digital phase detector for a fractional-N PLL is proposed and demonstrated and a digital sampling scheme that enables FSK modulation rates much larger than the loop bandwidth is demonstrated, without compromising on the frequency accuracy of the output signal.