We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

/pdf/all-digital-pll-and-transmitter-for-mobile-phones-2mf5fxyzjo.pdf

All-digital PLL and transmitter for mobile phones

https://calhoun.nps.edu/bitstream/10945/24839/1/singlesidebandtr00elli.pdf

Single sideband transmission by envelope elimination and restoration.

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

A digitally modulated power amplifier (DPA) in 1.2 V 0.13 mum SOI CMOS is presented, to be used as a building block in multi-standard, multi-band polar transmitters. It performs direct amplitude modulation of an input RF carrier by digitally controlling an array of 127 unary-weighted and three binary-weighted elementary gain cells. The DPA is based on a novel two-stage topology, which allows seamless operation from 800 MHz through 2 GHz, with a full-power efficiency larger than 40% and a 25.2 dBm maximum envelope power. Adaptive digital predistortion is exploited for DPA linearization. The circuit is thus able to reconstruct 21.7 dBm WCDMA/EDGE signals at 1.9 GHz with 38% efficiency and a higher than 10 dB margin on all spectral specifications. As a result of the digital modulation technique, a higher than 20.1 % efficiency is guaranteed for WCDMA signals with a peak-to-average power ratio as high as 10.8 dB. Furthermore, a 15.3 dBm, 5 MHz WiMAX OFDM signal is successfully reconstructed with a 22% efficiency and 1.53% rms EVM. A high 10-bit nominal resolution enables a wide-range TX power control strategy to be implemented, which greatly minimizes the quiescent consumption down to 10 mW. A 16.4% CDMA average efficiency is thus obtained across a > 70 dB power control range, while complying with all the spectral specifications.

A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control

An enhanced data-rates for GSM evolution (EDGE) transmitter using a nonlinear GSM-type PA is presented. It is based on a novel polar loop architecture that employs separate feedback control of the amplitude and the phase of the output signal. With this approach, the problems with AM-to-PM as well as AM-to-AM of the nonlinear PA are essentially eliminated. In addition, this architecture allows for a large dynamic output power control range, as required by the GSM specification. The transmitter uses a standard I/Q interface and does not require the extraction of amplitude and phase modulation in the digital domain. The dual feedback loop ensures robust performance even under voltage-standing wave ratio variations without using an isolator. No external PA filtering is required to meet the transmitter noise in the receive band. The EDGE spectral mask is met with an rms error vector magnitude of <3% at 29 dBm at the antenna, corresponding to 2 dB above nominal maximum output power. There is no mode change between GMSK and EDGE, and the transmitter operates seamlessly in multislot Enhanced General Packet Radio Service. The polar modulation transmitter meets or exceeds the GSM-type approval requirements for both EDGE and GMSK in quad band (850/900/1800/1900 MHz).

Quad-band GSM/GPRS/EDGE polar loop transmitter

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.

A polar modulator transmitter for GSM/EDGE

We describe a 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling (dynamic) and memory errors. An effective dithering technique is embedded in the calibration signal to break the dependence of the calibration on the input signal amplitude. In addition, to improve the sampling linearity, the ADC employs input distortion cancellation and another digital calibration to compensate for the non-linear charge injection (kickback) from the sampling capacitors on the input driver. The ADC is fabricated in a 65nm CMOS process and has an integrated input buffer. With a 140MHz and 2Vpp input signal, the SNR is 69dB, the SFDR is 86dB, and the power is 1.2W.

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

Data transmitter embodiments are provided which are particularly useful as interface devices for accurate and reliable transmittal of data from high-speed data system devices such as analog-to-digital converters. Transmitter embodiments have been found to provide excellent fidelity of data transfer at high data rates (e.g., 4 gigabits/second) while consuming only a portion of the power of many conventional transmitters and requiring only a portion of the layout area of these transmitters. Transmitter embodiments provide effective control of transmitter parameters such as matched impedances, data symmetry, common-mode level, data eye and current drain.

High-speed data transmitters

Clock generator embodiments are provided to generate half-rate I and Q clock signals. The generators are configured to insure fan-out limitations, to insure correct phasing at startup, to reduce the number of signal inverters in a critical path, and to reduce the total number of inverter structures to thereby substantially extend generator operational frequency. An exemplary generator embodiment requires only two tri-state inverters and four inverters. These clock generators are particularly suited for variety of electronic systems such as high speed data serializers.

Clock generators for generation of in-phase and quadrature clock signals

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

Brad P. Jeffries

Papers

A polar modulator transmitter for GSM/EDGE

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

High-speed data transmitters

Clock generators for generation of in-phase and quadrature clock signals

Frequency synthesizer with dynamic phase and pulse-width control