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Brad P. Jeffries
Researcher at Analog Devices
Publications - 10
Citations - 206
Brad P. Jeffries is an academic researcher from Analog Devices. The author has contributed to research in topics: Digital clock manager & Signal. The author has an hindex of 5, co-authored 10 publications receiving 204 citations.
Papers
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Journal ArticleDOI
A polar modulator transmitter for GSM/EDGE
Michael R. Elliott,Tony Montalvo,Frank Murden,Brad P. Jeffries,Jonathan Richard Strange,S. Atkinson,A. Hill,S. Nandipaku,J. Harrebek +8 more
TL;DR: This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters.
Proceedings ArticleDOI
29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration
Ahmed Mohamed Abdelatty Ali,Huseyin Dinc,Paritosh Bhoraskar,Christopher Daniel Dillon,Scott Puckett,Bryce Gray,Carroll C. Speir,Jonathan Lanford,David Jarman,Janet Brunsilius,Peter Derounian,Brad P. Jeffries,Ushma Mehta,Matt McShea,Ho-Young Lee +14 more
TL;DR: A 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling, settling and memory errors and an effective dithering technique is embedded in the calibration signal to break the dependence of the calibration on the input signal amplitude.
Patent
High-speed data transmitters
TL;DR: In this paper, the authors present a data transmitter embodiment for accurate and reliable transmittal of data from high-speed data system devices such as analog-to-digital converters.
Patent
Clock generators for generation of in-phase and quadrature clock signals
TL;DR: In this paper, clock generators are presented to generate half-rate I and Q clock signals for high-speed data serializers, and the generators are configured to insure fan-out limitations, to insure correct phasing at startup, and to reduce the number of signal inverters in a critical path.
Patent
Frequency synthesizer with dynamic phase and pulse-width control
Oscar Sebastian Burbano,Matthew D. McShea,Peter Derounian,Reuben P. Nelson,Ziwei Zheng,Brad P. Jeffries +5 more
TL;DR: In this article, an agile frequency synthesizer with dynamic phase and pulsewidth control is described, which includes a count circuit configured to modify a stored count value by an adjustment value, and an output clock generator with rising and falling edges that are based at least in part on the stored value satisfying a count threshold.