Electrowetting has become one of the most widely used tools for manipulating tiny amounts of liquids on surfaces. Applications range from 'lab-on-a-chip' devices to adjustable lenses and new kinds of electronic displays. In the present article, we review the recent progress in this rapidly growing field including both fundamental and applied aspects. We compare the various approaches used to derive the basic electrowetting equation, which has been shown to be very reliable as long as the applied voltage is not too high. We discuss in detail the origin of the electrostatic forces that induce both contact angle reduction and the motion of entire droplets. We examine the limitations of the electrowetting equation and present a variety of recent extensions to the theory that account for distortions of the liquid surface due to local electric fields, for the finite penetration depth of electric fields into the liquid, as well as for finite conductivity effects in the presence of AC voltage. The most prominent failure of the electrowetting equation, namely the saturation of the contact angle at high voltage, is discussed in a separate section. Recent work in this direction indicates that a variety of distinct physical effects?rather than a unique one?are responsible for the saturation phenomenon, depending on experimental details. In the presence of suitable electrode patterns or topographic structures on the substrate surface, variations of the contact angle can give rise not only to continuous changes of the droplet shape, but also to discontinuous morphological transitions between distinct liquid morphologies. The dynamics of electrowetting are discussed briefly. Finally, we give an overview of recent work aimed at commercial applications, in particular in the fields of adjustable lenses, display technology, fibre optics, and biotechnology-related microfluidic devices.

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Electrowetting: from basics to applications

The computational brain: Patricia S. Churchland and Terrence J. Sejnowski (MIT Press, Cambridge, MA, 1992); xi, 544 pages, $39.95

Guided by brain-like ‘spiking’ computational frameworks, neuromorphic computing—brain-inspired computing for machine intelligence—promises to realize artificial intelligence while reducing the energy requirements of computing platforms. This interdisciplinary field began with the implementation of silicon circuits for biological neural routines, but has evolved to encompass the hardware implementation of algorithms with spike-based encoding and event-driven representations. Here we provide an overview of the developments in neuromorphic computing for both algorithms and hardware and highlight the fundamentals of learning and hardware frameworks. We discuss the main challenges and the future prospects of neuromorphic computing, with emphasis on algorithm–hardware codesign. The authors review the advantages and future prospects of neuromorphic computing, a multidisciplinary engineering concept for energy-efficient artificial intelligence with brain-inspired functionality.

Towards spike-based machine intelligence with neuromorphic computing.

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

This paper discusses connectivity between neuromorphic chips, which use the timing of fixed-height fixed-width pulses to encode information. Address-events (log/sub 2/(N)-bit packets that uniquely identify one of N neurons) are used to transmit these pulses in real time on a random-access time-multiplexed communication channel. Activity is assumed to consist of neuronal ensembles-spikes clustered in space and in time. This paper quantifies tradeoffs faced in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and concludes that an arbitered channel design is the best choice. The arbitered channel is implemented with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, it is shown how the overhead of arbitrating, and encoding and decoding, can be reduced in area (from N to /spl radic/N) by organizing neurons into rows and columns, and reduced in time (from log/sub 2/(N) to 2) by exploiting locality in the arbiter tree and in the row-column architecture, and clustered activity. Throughput is boosted by pipelining and by reading spikes in parallel. Simple techniques that reduce crosstalk in these mixed analog-digital systems are described.

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Point-to-point connectivity between neuromorphic chips using address events

We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its dc operating point adaptively. Because the hot-electron injection is an inherent part of the pFET's behavior, we obtain this adaptation with no additional circuitry. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high-frequency cutoff is controlled electronically, as is done in continuous-time filters. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data for a wide range of operating conditions and input waveforms. This autozeroing floating-gate amplifier demonstrates how to use continuous-time floating-gate adaptation in amplifier design.

/pdf/an-autozeroing-floating-gate-amplifier-41c6zmvm1j.pdf

An autozeroing floating-gate amplifier

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells.

A CMOS programmable analog memory-cell array using floating-gate circuits

We describe single-transistor silicon synapses that compute, learn, and provide non-volatile memory retention. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and the weight value, and update the weight value according to a Hebbian or a backpropagation learning rule. Memory is accomplished via charge storage on polysilicon floating gates, providing long-term retention without refresh. The synapses efficiently use the physics of silicon to perform weight updates; the weight value is increased using tunneling and the weight value decreases using hot electron injection. The small size and low power operation of single transistor synapses allows the development of dense synaptic arrays. We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current. The synaptic array was fabricated in the standard 2µm double - poly, analog process available from MOSIS.

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Single Transistor Learning Synapses

In this paper, we describe our floating-gate pFET device, with its many circuit applications and supporting experimental measurements. We developed these devices in standard double-poly CMOS technologies by utilizing many effects inherent in these processes. We add floating-gate charge by electron tunneling, and we remove floating-gate charge by hot-electron injection. With this floating-gate technology, we cannot only build analog EEPROMs, we can also implement adaptation and learning when we consider floating-gate devices to be circuit elements with important time-domain dynamics. We start by discussing non-adaptive properties of floating-gate devices and we present two representative non-adaptive applications. First, we discuss using the floating-gate pFETs as non-volatile voltage sources or potentiometers (e-pots). Second, we discuss using floating-gate pFETs to build translinear circuits that compute the product of powers of the input currents. We then discuss the physics, behavior, and applications of adaptation using floating-gate pFETs. The physics of adaptation starts with floating-gate pFETs with continuous tunneling and injection currents. A single floating-gate MOS device operating with continuous-time tunneling and injection currents can exhibit either stabilizing or destabilizing behaviors. One particular application is an autozeroing floating-gate amplifier (AFGA) that uses tunneling and pFET hot-electron injection to adaptively set its DC operating point. Continuous-time circuits comprising multiple floating-gate MOS devices show various competitive and cooperative behaviors between devices. These floating-gate circuits can be used to build silicon systems that adapt and learn.

Adaptive circuits using pFET floating-gate devices

We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2μm double-poly p-well process through MOSIS.

Bradley A. Minch

Papers

An autozeroing floating-gate amplifier

A CMOS programmable analog memory-cell array using floating-gate circuits

Single Transistor Learning Synapses

Adaptive circuits using pFET floating-gate devices

Translinear circuits using subthreshold floating-gate MOS transistors