B
Brian Greskamp
Researcher at University of Illinois at Urbana–Champaign
Publications - 13
Citations - 854
Brian Greskamp is an academic researcher from University of Illinois at Urbana–Champaign. The author has contributed to research in topics: Microarchitecture & Overhead (computing). The author has an hindex of 8, co-authored 12 publications receiving 830 citations.
Papers
More filters
Journal ArticleDOI
VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects
TL;DR: In this paper, a microarchitecture-aware model for process variation is proposed, including both random and systematic effects, and the model is specified using a small number of highly intuitive parameters.
Proceedings ArticleDOI
EVAL: Utilizing processors with variation-induced timing errors
TL;DR: An effective technique to maximize performance and minimize power in the presence of variation-induced errors, namely High-Dimensional dynamic adaptation is introduced, which increases processor frequency by 56% on average, allowing the processor to cycle 21% faster than without variation.
Proceedings ArticleDOI
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
Brian Greskamp,Josep Torrellas +1 more
TL;DR: This paper presents the Paceline leader-checker microarchitecture, a leader core that runs the thread at higher-than-rated frequency, while passing execution hints and prefetches to a safely-clocked checker core in the same chip multiprocessor.
Proceedings ArticleDOI
Blueshift: Designing processors for timing speculation from the ground up.
Brian Greskamp,Lu Wan,Ulya R. Karpuzcu,Jeffrey J. Cook,Josep Torrellas,Deming Chen,Craig Zilles +6 more
TL;DR: This paper presents a new approach where the processor itself is designed from the ground up for Timing Speculation, and introduces two techniques that, when applied under BlueShift, improve processor performance: On-demand Selective Biasing (OSB) and Path Constraint Tuning (PCT).
Proceedings ArticleDOI
The BubbleWrap many-core: popping cores for sequential acceleration
TL;DR: This paper proposes Dynamic Voltage Scaling for Aging Management (DVSAM) - a new scheme for managing processor aging to attain higher performance or lower power consumption and introduces the BubbleWrap many-core, a novel architecture that makes extensive use of DVSAM.