Bruno Azeredo

TL;DR: A top-down fabrication method that involves the combination of superionic-solid-state-stamping (S4) patterning with metal-assisted-chemical-etching (MacEtch) to produce silicon nanowire arrays with defined geometry and optical properties in a manufacturable fashion is reported.

TL;DR: In this article, a two-step metal assisted chemical etching technique is used to systematically vary the sidewall roughness of Si nanowires in vertically aligned arrays, and the thermal conductivities of nanowire arrays are studied using time domain thermoreflectance and compared to their high-resolution transmission electron microscopy determined roughness.

TL;DR: It is found that the porosity decreases from top to bottom along the axial direction and increases with etching time, and with a MacEtch solution that has a high [HF]:[H(2)O(2)] ratio and low temperature, it is possible to form completely solid nanowires with aspect ratios of less than approximately 10:1.

TL;DR: This paper presents a non-lithographic approach to generate wafer-scale single crystal silicon nanowires (SiNWs) with controlled sidewall profile and surface morphology and a post-fabrication roughening step is added to the approach.

TL;DR: Using experimentally characterized surface roughness, it is shown that a multiple scattering theory provides excellent agreement and explanation of the observed low-temperature dependence of rough surface nanowires, and advances applications of nanoweires in thermoelectric energy conversion.