[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

Rapid progress in the synthesis and processing of materials with structure on nanometer length scales has created a demand for greater scientific understanding of thermal transport in nanoscale devices, individual nanostructures, and nanostructured materials. This review emphasizes developments in experiment, theory, and computation that have occurred in the past ten years and summarizes the present status of the field. Interfaces between materials become increasingly important on small length scales. The thermal conductance of many solid–solid interfaces have been studied experimentally but the range of observed interface properties is much smaller than predicted by simple theory. Classical molecular dynamics simulations are emerging as a powerful tool for calculations of thermal conductance and phonon scattering, and may provide for a lively interplay of experiment and theory in the near term. Fundamental issues remain concerning the correct definitions of temperature in nonequilibrium nanoscale systems. Modern Si microelectronics are now firmly in the nanoscale regime—experiments have demonstrated that the close proximity of interfaces and the extremely small volume of heat dissipation strongly modifies thermal transport, thereby aggravating problems of thermal management. Microelectronic devices are too large to yield to atomic-level simulation in the foreseeable future and, therefore, calculations of thermal transport must rely on solutions of the Boltzmann transport equation; microscopic phonon scattering rates needed for predictive models are, even for Si, poorly known. Low-dimensional nanostructures, such as carbon nanotubes, are predicted to have novel transport properties; the first quantitative experiments of the thermal conductivity of nanotubes have recently been achieved using microfabricated measurement systems. Nanoscale porosity decreases the permittivity of amorphous dielectrics but porosity also strongly decreases the thermal conductivity. The promise of improved thermoelectric materials and problems of thermal management of optoelectronic devices have stimulated extensive studies of semiconductor superlattices; agreement between experiment and theory is generally poor. Advances in measurement methods, e.g., the 3ω method, time-domain thermoreflectance, sources of coherent phonons, microfabricated test structures, and the scanning thermal microscope, are enabling new capabilities for nanoscale thermal metrology.

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Nanoscale thermal transport

Electronic devices have advanced from their heavy, bulky origins to become smart, mobile appliances. Nevertheless, they remain rigid, which precludes their intimate integration into everyday life. Flexible, textile and stretchable electronics are emerging research areas and may yield mainstream technologies. Rollable and unbreakable backplanes with amorphous silicon field-effect transistors on steel substrates only 3 μm thick have been demonstrated. On polymer substrates, bending radii of 0.1 mm have been achieved in flexible electronic devices. Concurrently, the need for compliant electronics that can not only be flexed but also conform to three-dimensional shapes has emerged. Approaches include the transfer of ultrathin polyimide layers encapsulating silicon CMOS circuits onto pre-stretched elastomers, the use of conductive elastomers integrated with organic field-effect transistors (OFETs) on polyimide islands, and fabrication of OFETs and gold interconnects on elastic substrates to realize pressure, temperature and optical sensors. Here we present a platform that makes electronics both virtually unbreakable and imperceptible. Fabricated directly on ultrathin (1 μm) polymer foils, our electronic circuits are light (3 g m(-2)) and ultraflexible and conform to their ambient, dynamic environment. Organic transistors with an ultra-dense oxide gate dielectric a few nanometres thick formed at room temperature enable sophisticated large-area electronic foils with unprecedented mechanical and environmental stability: they withstand repeated bending to radii of 5 μm and less, can be crumpled like paper, accommodate stretching up to 230% on prestrained elastomers, and can be operated at high temperatures and in aqueous environments. Because manufacturing costs of organic electronics are potentially low, imperceptible electronic foils may be as common in the future as plastic wrap is today. Applications include matrix-addressed tactile sensor foils for health care and monitoring, thin-film heaters, temperature and infrared sensors, displays, and organic solar cells.

An ultra-lightweight design for imperceptible plastic electronics

Modeling chemical and physical processes of wood and biomass pyrolysis

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin body, FinFET, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomena including ballistic electron transport, which reshapes the heat generation region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. This paper surveys trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems

Heat Generation and Transport in Nanometer-Scale Transistors

A two-step metal assisted chemical etching technique is used to systematically vary the sidewall roughness of Si nanowires in vertically aligned arrays. The thermal conductivities of nanowire arrays are studied using time domain thermoreflectance and compared to their high-resolution transmission electron microscopy determined roughness. The thermal conductivity of nanowires with small roughness is close to a theoretical prediction based on an upper limit of the mean-free-paths of phonons given by the nanowire diameter. The thermal conductivity of nanowires with large roughness is found to be significantly below this prediction. Raman spectroscopy reveals that nanowires with large roughness also display significant broadening of the one-phonon peak; the broadening correlates well with the reduction in thermal conductivity. The origin of this broadening is not yet understood, as it is inconsistent with phonon confinement models, but could derive from microstructural changes that affect both the optical phonons observed in Raman scattering and the acoustic phonons that are important for heat conduction.

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Thermal conductivity of silicon nanowire arrays with controlled roughness

We report the fabrication of degenerately doped silicon (Si) nanowires of different aspect ratios using a simple, low-cost and effective technique that involves metal-assisted chemical etching (MacEtch) combined with soft lithography or thermal dewetting metal patterning. We demonstrate sub-micron diameter Si nanowire arrays with aspect ratios as high as 180:1, and present the challenges in producing solid nanowires using MacEtch as the doping level increases in both p- and n-type Si. We report a systematic reduction in the porosity of these nanowires by adjusting the etching solution composition and temperature. We found that the porosity decreases from top to bottom along the axial direction and increases with etching time. With a MacEtch solution that has a high [HF]:[H2O2] ratio and low temperature, it is possible to form completely solid nanowires with aspect ratios of less than approximately 10:1. However, further etching to produce longer wires renders the top portion of the nanowires porous. (Some figures may appear in colour only in the online journal)

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Porosity control in metal-assisted chemical etching of degenerately doped silicon nanowires

Molybdenum disulfide (MoS2), a two-dimensional material purchased from SPI supplies, was analyzed using high-resolution X-ray photoelectron spectroscopy (XPS). A flake was mechanically exfoliated from a MoS2 bulk single crystal for the study. The XPS spectra of MoS2 obtained using monochromatic Al Kα radiation at 0.83401 nm include a survey scan, high-resolution spectra of O 1s, Mo 3p, C 1s, Mo 3d, S 2s, S 2p, Mo 4s, Mo 4p, S 3s, and valance band. Extended energy ranges were collected in the vicinity of the Mo 3d/S 2s, S 2p, and Mo 4s/Mo 4p/S 3s/Valence band regions allowing for fitting of surface plasmon features and determination of Tougaard scattering cross-section parameters. Quantitative analysis indicates a surface composition of MoS1.9.

2-D Material Molybdenum Disulfide Analyzed by XPS

The Fourier law for lattice heat conduction fails when the source of heat is small compared to the phonon mean free path. We provide experimental evidence for this effect using heating and electrical-resistance thermometry along a doped region in a suspended silicon membrane. The data are consistent with a closed-form two-fluid phonon conduction model, which accounts for the severe departure from equilibrium at the hotspot. The temperature rise exceeds predictions based on the Fourier law by 60% when the phonon mean free path is a factor of 30 larger than the resistor thickness. This work is improving the constitutive modeling of heat flow in deep-submicron transistors.

https://nanoheat.stanford.edu/sites/default/files/publications/A47.pdf

Sanjiv Sinha

Papers

Heat Generation and Transport in Nanometer-Scale Transistors

Thermal conductivity of silicon nanowire arrays with controlled roughness

Porosity control in metal-assisted chemical etching of degenerately doped silicon nanowires

2-D Material Molybdenum Disulfide Analyzed by XPS

Measurement of ballistic phonon conduction near hotspots in silicon