Showing papers by "Bumman Kim published in 2014"

Apparatus and method for matching harmonics

Abstract: An apparatus of a power amplifier is provided. The apparatus includes an input boosting circuit configured to match a second harmonic input signal using a harmonic control circuit of an input stage to maximize an efficiency and an output power, a die cell configured to receive and amplify an output signal of the input boosting circuit, and an output boosting circuit configured to receive an output signal of the die cell and to match a second harmonic output signal of the output signal of the die cell using a harmonic control circuit of an output stage to maximize the efficiency and the output power.

Linear Doherty Power Amplifier With an Enhanced Back-Off Efficiency Mode for Handset Applications

Abstract: This paper presents a linear Doherty power amplifier (PA) with enhanced back-off efficiency mode for handset applications. For linear Doherty operation, we analyze the gain modulation as well as the cancellation of the third-order intermodulation distortion in order to improve the linearity. A compact design method is also discussed to implement on a single chip for a handset. The proposed Doherty PA delivers good performance with regard to the third-generation (3G)/fourth-generation (4G) modulation signals. A switched-load power-mode PA is adopted in the proposed Doherty PA to enhance the efficiency in the low-power region with over 10-dB back-off. For demonstration purposes, the PA is implemented using an InGaP/GaAs heterojunction bipolar transistor and AlGaAs/InGaAs pseudomorphic high electron-mobility transistor process. The PA is tested at 1.85 GHz using both a long-term evolution signal with 16-quadrature amplitude modulation, 7.5-dB peak-to-average power ratio, and 10-MHz bandwidth (BW) and a wideband code division multiple access signal with 3.3-dB PAPR and 3.84-MHz BW. The proposed linear Doherty PA with an enhanced back-off efficiency mode delivers good performance in both the high- and low-power modes, implying that the dual-power-mode Doherty PA configuration can be a promising candidate for extending the battery life of handheld devices in 3G and 4G wireless communication systems.

A 2.14-GHz GaN MMIC Doherty Power Amplifier for Small-Cell Base Stations

Abstract: A novel 2.14-GHz Doherty power amplifier (PA) was designed and fabricated using a 0.25- μm GaN on SiC monolithic microwave integrated circuit (MMIC), to build small-cell base stations. To reduce the size and loss, lumped passive elements were employed in a manner of minimizing the device count. The core components of the PA were integrated on the MMIC die to reduce the area, and low-loss chip inductors were mounted around the die to enhance the efficiency. An unconventional uneven power splitting was also used to enhance the performance. For a continuous wave, a 2-dB-gain-compression power of 40.5 dBm was obtained with a drain efficiency (DE) of 60.4%. At 7.3-dB backed-off power, a DE of 52.2% was obtained with a power gain of 15.7 dB. When a 10-MHz-bandwidth long-term evolution signal with 7.1-dB peak-to-average power ratio was applied, an adjacent channel leakage ratio (ACLR) of -34.7 dBc with a DE of 51.8% was achieved at an average power of 33.2 dBm. After a digital pre-distortion process, the ACLR and DE were improved to -49.6 dBc and 52.7%, respectively.

Analysis of Envelope-Tracking Power Amplifier Using Mathematical Modeling

Abstract: This paper describes analysis of an envelope-tracking power amplifier (ET PA) to show its operational behavior. The RF PA is modeled by sweeping the input power and supply voltage. The RF PA model is composed of three 2-D lookup tables including the amplitude-to-amplitude modulation, amplitude-to-phase modulation, and amplitude-to-efficiency modulation. The hybrid switching supply modulator is also modeled using an ideal op-amp, ideal switches, and other assisting blocks. Based on the mathematical models of the RF PA and supply modulator, the ET PA can be analyzed with a fast calculation speed and a good accuracy to find the optimum ET operation point. A power control strategy is presented for the optimal ET operation over a broad output power range. The effect of the delay mismatch on the characteristics of the ET PA is also described to assist the time alignment algorithm. For a 10-MHz long-term evolution signal with a 7.44-dB PAPR, the implemented ET PA at 1.71 GHz delivers a PAE of 44.3%, a gain of 29 dB, an evolved universal terrestrial radio access adjacent channel leakage ratio of ${-}{\hbox{35.1 }}$ dBc, and an error vector magnitude of 2.91% at an average output power of 28 dBm.

CMOS Saturated Power Amplifier With Dynamic Auxiliary Circuits for Optimized Envelope Tracking

Abstract: A CMOS saturated power amplifier (PA) is developed for optimally implementing the envelope-tracking (ET) transmitter. The CMOS saturated PA is used to maximize the efficiency of the ET PA. The dynamic feedback control and the biasing techniques at the gates of the common-gate stage and the common-source of the cascode structure are proposed to improve the dynamic range, linearity and efficiency. The fully-integrated CMOS PA with a supply modulator is fabricated using a 0.18- μm RF CMOS technology. For a long-term evolution signal at 1.85 GHz with a 10-MHz bandwidth and a 16-quadrature amplitude modulation 7.5 dB peak-to-average power ratio, the ET-based CMOS PA module delivers a power-added efficiency of 37.6%, an error vector magnitude of 2.4%, and an an evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE-UTRA) of -36.8 dBc at an average output power of 26.5 dBm. The proposed auxiliary circuits enable the ET-based CMOS PA to provide the significantly improved performance.

Broadband Saturated Power Amplifier With Harmonic Control Circuits

Abstract: This letter presents a broadband saturated power amplifier (PA) using the harmonic control circuits for base station application. The saturated PA has advantages for broadband operation with high efficiency due to the large tolerance of the second harmonic tuning. However, it is difficult to simultaneously achieve the fundamental and second harmonic impedance matching across a wide bandwidth. To solve the problem, the harmonic control circuits are placed at the input and output of the device's die. These harmonic control circuits play a role of leading the second harmonic impedances to the optimum regions but are specially designed to be insensitive to the following fundamental matching circuit. The saturated PA with the harmonic control circuit is designed using a 120 W GaN device, achieving a high efficiency and wide bandwidth characteristics simultaneously. The measured output power, drain efficiency, and gain are at least 51.0 dBm, 71.0%, and 8.22 dB at the saturation across the 1.75 to 2.17 GHz (21% relative bandwidth) under pulse test (10% duty). This saturated PA also delivers good performances for long term evolution (LTE) and wideband code division multiple access (WCDMA) modulated signals at 1.85 and 2.14 GHz, respectively. These results show that the broadband saturated PA with the harmonic control circuit is suitable to wide bandwidth multimode/multiband applications.

CMOS Linear Power Amplifier with Envelope Tracking Operation

Abstract: A differential-cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented by 0.18 μm RF CMOS technology. The loss at the output is minimized by implementing the output transformer on a FR-4 printed circuit board (PCB). The CMOS PA utilizes the 2 nd harmonic short at the input to enhance the linearity. The measurement was done by the 10MHz bandwidth 16QAM 6.88 dB peak-to-average power ratio long-term evolution (LTE) signal at 1.85 GHz. The ET operation of the CMOS PA with the supply modulator enhances the power-added efficiency (PAE) by 2.5, to 10% over the stand-alone CMOS PA for the LTE signal. The ET PA achieves a PAE of 36.5% and an ACLRE-UTRA of ?32.7 dBc at an average output power of 27 dBm.

Fully Integrated CMOS Saturated Power Amplifier With Simple Digital Predistortion

Abstract: A highly efficient CMOS saturated power amplifier (PA) is implemented. The efficiency is enhanced by the voltage waveform engineering using the second harmonic component generated by the nonlinear output capacitor (C out ). For an improved linearity to satisfy the specification of handset applications, a simple open-loop digital predisortion algorithm is employed. The fully integrated single-stage differential PA including the output transformer is fabricated using a 0.18- μm CMOS process. The PA with 3.5 V supply delivers good performance across the 1.7-2.0 GHz frequency band.

Complementary metal-oxide semiconductor doherty power amplifier based on voltage combining method

Abstract: A 1.75 GHz Doherty power amplifier (PA) is designed and implemented in a 0.18-μm complementary metal-oxide semiconductor (CMOS) process. This Doherty PA uses a voltage combining transformer to combine the output power and realise the load modulation which is different from conventional current combining Doherty amplifiers. The prototype has a power-added efficiency (PAE) of 31.6% at a maximum output power of 28.6 dBm from 3.4 V supply voltage. The PAE at 6 dB back-off is still high, about 25%. It shows clearly the efficiency enhancement at the power back-off point because of the Doherty operation. This is the first use of voltage combining techniques in CMOS Doherty PA design.

Optimised Doherty power amplifier with auxiliary peaking cell

Abstract: The Doherty power amplifier has the most attractive architecture to improve the efficiency for amplifying a signal with a high peak-to-average power ratio. However, the ideal Doherty operation is difficult to be achieved because the g m of the peaking amplifier should be two times larger than that of the carrier amplifier. The g m mismatch between the carrier and peaking amplifiers hinders the proper load modulation at the peak power region. The Doherty power amplifier with an auxiliary drive cell for the peaking amplifier is introduced to solve the problem. The auxiliary peaking cell drives the main peaking amplifier with higher input power, solving the gain and output power reduction problem. Experimental results show that the proposed Doherty power amplifier can enhance gain, output power and power-added efficiency.

Transformer based dual-power-mode CMOS power amplifier for handset applications

Abstract: A fully integrated transformer based dual-power-mode CMOS power amplifier (PA) is implemented. The proposed architecture provides enhanced back-off efficiency with simple circuit topology. With broadband characteristic of the transmission line transformer, the PA delivers good performance across the 1.7–2.0 GHz frequency band. The PA with a 3.5 V supply voltage has gains of 14.5–16.2 dB and 10–10.5 dB in high power mode (HPM) and low power mode (LPM), respectively. The linear average output power for long-term evolution signals having 10-MHz bandwidth and 7.5 dB peak-to-average power ratio is 26/20 dBm with a PAE of 31.6%–33.8%/20.8%–26.5% across the 1.7–2.0 GHz frequency in the HPM/LPM.

Dynamic feedback and biasing for a linear CMOS power amplifier with envelope tracking

Abstract: This paper presents a fully integrated CMOS power amplifier (PA) with a dynamic feedback and gate biasing. The two dynamic circuits improve the linearity and efficiency of the stand-alone PA and ET PA. The proposed CMOS ET PA including the dynamic control circuits is fabricated using 0.18-μm CMOS process. For a long-term evolution (LTE) signal at 1.85 GHz with a 10-MHz bandwidth and a 16-QAM 7.5 dB PAPR, the CMOS envelope tracking (ET) PA module achieves a power-added efficiency (PAE) of 35.4%, an error vector magnitude (EVM) of 3.6%, and an ACLR E-UTRA of -33.3 dBc at an average output power of 26.5 dBm. The ET PA with the control circuits improves the gain deviation within 2 dB and the PAE up to 5%, respectively, according to the output power level, over those of the ET PA without the dynamic control for the same LTE signal.

Highly Linear 2-stage Doherty Power Amplifier Using GaN MMIC

Abstract: A power amplifier (PA) for a femto-cell base station should be highly efficient, linear and small. The efficiency for amplification of a high peak-to-average power ratio (PAPR) signal was improved by designing an asymmetric Doherty PA (DPA). The linearity was improved by applying third-order inter-modulation (IM3) cancellation method. A small size is achieved by designing the DPA using GaN MMIC process. The implemented 2-stage DPA delivers a power-added efficiency (PAE) of 38.6% and a gain of 33.4 dB with an average power of 34.2 dBm for a 7.2 dB PAPR 10 MHz bandwidth LTE signal at 2.14 GHz.

Wideband envelope amplifier for envelope-tracking operation of handset power amplifier

Abstract: This paper presents a wideband envelope amplifier for envelope-tracking operation of handset power amplifiers. The amplifier has a combined structure composed of a linear regulator and a switching converter. A low output impedance class-AB push-pull output stage is employed to expand the bandwidth (BW) of the linear regulator. By reducing the output resistance of the source follower using dual shunt feedbacks, a nondominant pole at the gate of the output buffer is pushed to the higher frequency range. The gain BW product (GBW) of the linear regulator is improved without sacrificing the phase margin (PM) and efficiency. The designed linear regulator achieves the GBW of 129.6-MHz and PM of 73.1°. For a 40-MHz long term evolution signal having a peak-to-average power ratio of 7.4 dB, the envelope amplifier delivers an efficiency of 73.6% at the peak power driving a 7.7Ω resistive load.

Advanced design of differential CMOS PA

Abstract: A fully-integrated differential cascode linear CMOS power amplifier (PA) with adaptive gate bias circuits is reported. The active bias circuits are employed to achieve a high linearity from a deep class-AB biased common-source stage. The gate bias of the common-gate stage is adapted to linearize the severe distortion of the deep biased amplifier at a low power region. An envelope signal is injected at the gate of CS stage to linearize the amplifier further. The IMD3 asymmetry created by the memory effect due to the bias controls is suppressed using the second harmonic short circuits at the virtual grounding points. The proposed single stage PA including the bias circuit is fabricated using 0.18-m RF CMOS technology. The linear PA delivers the expected performance of high efficiency across a broad bandwidth using a wide audio band signal.

Broadband operation of saturated amplifier with high efficiency

Abstract: A saturated operation of a power amplifier with the proper harmonic tuning can be highly efficient. The harmonics, mainly the second harmonic, are generated internally by the saturation operation. Matching tolerance for the harmonic tuning is very large and can be operated across a broadband with a high efficiency. Based on the saturated amplifier, we have realized a broadband amplifier using GaN device. Across the 1.75-2.17 GHz band, the output power, drain efficiency, and gain are between 51.0-52.3 dBm, 71.0-84.4%, and 8.22-11.6 dB, respectively.