Byung-Geun Lee

TL;DR: A neuromorphic system for visual pattern recognition realized in hardware and presented and implemented with passive synaptic devices based on modified spike-timing-dependent plasticity, which has been successfully demonstrated by training and recognizing number images from 0 to 9.

TL;DR: Feasibility of a high speed pattern recognition system using 1k-bit cross-point synaptic RRAM array and CMOS-based neuron chip has been experimentally demonstrated and learning capability of a neuromorphic system comprising RRAM synapses andCMOS neurons has been confirmed experimentally, for the first time.

TL;DR: The proposed PCMO-based memristive synapse exhibits the necessary gradual and symmetrical conductance changes, and has been successfully adapted to a neural network system that is likely to intrigue many researchers and stimulate a new research direction.

TL;DR: The fabrication, modeling and implementation of nanoscale RRAM with multi-level storage capability for an electronic synapse device is reported and the learning capabilities and predictable performance by a neuromorphic circuit composed of a nanoscales 1 kbit RRAM cross-point array of synapses and complementary metal-oxide-semiconductor neuron circuits are experimentally demonstrated.

TL;DR: The prototype ADC achieves low-power consumption and small die area by sharing an opamp between two successive pipeline stages by completely merging the front-end sample-and-hold amplifier into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique.